LDMOS Transistor with Dual-Work Function Gate for Breakdown Voltage
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Solution Overview
Problem
LDMOS transistors face challenges in achieving high breakdown voltage while maintaining low parasitic resistance due to the limitations of the n drift region, which affects their operational efficiency in applications such as automobiles, display electronics, and power converters.
Innovation Solution
The implementation of a second gate stack with a higher work function than the first gate stack, using a common gate electrode, and employing different high-k dielectric layers to increase breakdown voltage while minimizing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the n drift region is used to increase breakdown voltage by sustaining a larger depletion width, then breakdown voltage is improved, but parasitic resistance increases due to lower doped drain
Solution Approach 1:
The gate structure is segmented into a first gate electrode and a second gate electrode with different work functions. The first gate electrode (lower work function) controls the channel formation, while the second gate electrode (higher work function) controls the depletion region and breakdown voltage. This segmentation allows independent optimization of channel conductivity and breakdown characteristics, resolving the contradiction between low parasitic resistance and high breakdown voltage.
Solution Approach 2:
Different regions of the gate structure are assigned different work function qualities. The first gate electrode region has a lower work function to facilitate electron injection and reduce channel resistance, while the second gate electrode region has a higher work function to enhance the depletion width and increase breakdown voltage. This local quality differentiation enables simultaneous optimization of both parasitic resistance and breakdown voltage.
2Reliability
If a field plate is added to widen the depletion width and reduce peak electric field, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The field plate function is merged with the existing gate structure by adding a second gate electrode that is electrically connected to or integrated with the first gate electrode. This combination achieves the depletion width control and breakdown voltage enhancement of a field plate while maintaining a more compact and less complex device structure compared to a separate field plate implementation.
Solution Approach 2:
The second gate electrode serves multiple functions: it acts as a field plate to control the depletion region and enhance breakdown voltage, while also being integrated into the gate structure to maintain compactness. This multi-functionality reduces device complexity by eliminating the need for separate field plate components and their associated fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the breakdown voltage of LDMOS transistors while maintaining low parasitic resistance, improving their performance in various technological applications.
Implementation Method 1
having a common gate electrode with the gate stack, and having a higher work function than the gate stack
Implementation Method 2
employing different high-k dielectric layers to increase breakdown voltage while minimizing parasitic resistance
Data Source
AI summary
An LDMOS is formed with a second gate stack over n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.