LDMOS Dummy Gate Deep Well GIDL Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As LDMOS transistor dimensions decrease, gate-induced drain leakage (GIDL) current and substrate noise increase, leading to operation failures and reduced performance due to shorter component distances.
Innovation Solution
A semiconductor device with a dummy gate between the gate and drain region and a deep well region between the substrate and well regions is implemented to reduce GIDL current and substrate noise, featuring a five-terminal configuration with specific doping concentrations and isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If LDMOS transistor dimension is decreased, then device miniaturization is achieved, but GIDL current increases
Solution Approach 1:
A dummy gate structure is introduced as an intermediary element between the drain region and the active gate. This dummy gate acts as a mediator that modifies the electric field distribution in the drain region, thereby reducing the GIDL current generated by the high electric field at the drain-gate junction. The dummy gate does not directly control the channel but serves as a field-modifying structure that eliminates the harmful GIDL effect while allowing the device to maintain its miniaturized dimensions.
Solution Approach 2:
The dummy gate is specifically positioned only in the drain region where the GIDL current problem occurs, rather than uniformly across the entire device. This localized structure applies the quality change principle by modifying the electric field characteristics only in the critical drain region where high electric field induces GIDL current, while leaving other regions unchanged. The dummy gate creates a local potential well that redistributes carriers and reduces the high electric field concentration at the drain-gate junction.
2Volume of moving object
If LDMOS transistor dimension is decreased, then device miniaturization is achieved, but substrate noise increases
Solution Approach 1:
Deep well regions are introduced as intermediary structures between the active device regions and the substrate. These deep well regions act as noise isolation mediators that block the propagation of substrate noise to the device. The deep wells create potential barriers that prevent noise signals from the substrate from reaching the device, thereby isolating the device from substrate noise while maintaining the miniaturized device structure.
3Productivity
If component distance is shortened, then device integration is improved, but operation reliability deteriorates
Solution Approach 1:
The dummy gate and deep well regions serve as intermediary structures that enable short component distances while maintaining reliability. The dummy gate in the drain region prevents GIDL current that would otherwise cause operation failures, and the deep wells block substrate noise that would interfere with device operation. These intermediary structures allow the source, gate, and drain to be positioned closer together for better integration, while the intermediaries ensure reliable operation by eliminating the harmful effects that would result from the shortened distances.
Data Source
AI summary
Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.