LDMOS Transistor Edge Termination Removal for Compact Power Blocks
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Solution Overview
Problem
Conventional multi-finger LDMOS transistors have excessively large power blocks and high costs due to the inclusion of edge termination regions between adjacent devices, which are unnecessary and increase the size and cost of the device.
Innovation Solution
The solution involves omitting the edge termination regions between adjacent multi-finger LDMOS transistors by using shallow trench isolation (STI) structures in the isolation region, close to the gate field plate in the drift region, allowing for good isolation and high integration of active regions without the need for additional edge termination areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If edge termination regions are included in conventional multi-finger LDMOS transistors, then device isolation and reliability are improved, but the power block size and manufacturing cost increase excessively
Solution Approach 1:
The patent extracts and removes the edge termination regions from between adjacent device tips in multi-finger LDMOS transistors. By taking out these unnecessary regions, the power block size is reduced significantly while the core device isolation functionality is maintained through alternative isolation structures positioned at the periphery of the active region.
Solution Approach 2:
The patent merges the isolation function with the peripheral structure design by positioning isolation structures at the edges of the active region rather than requiring separate edge termination regions between each finger. This combining approach eliminates redundant structures and reduces overall device area.
2Reliability
If edge termination regions are formed between adjacent device tips, then device isolation is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the complex edge termination region formation process from the manufacturing sequence. By extracting this unnecessary step, the manufacturing process is simplified and cost is reduced while isolation is achieved through the streamlined peripheral isolation structure approach.
Solution Approach 2:
The patent applies isolation structures only where absolutely necessary - at the periphery of the active region - rather than uniformly between all adjacent fingers. This localized approach reduces manufacturing complexity by eliminating redundant processing steps in the center regions where isolation is not needed.
3Reliability
If multiple edge termination regions are included in limited-width multi-finger LDMOS transistors, then device isolation is maintained, but the active region integration density decreases
Solution Approach 1:
The patent merges multiple isolation functions into a single peripheral isolation structure design. By combining the isolation roles into edge-positioned structures rather than requiring separate termination regions between each finger, the active region integration density increases significantly while maintaining adequate device isolation.
Solution Approach 2:
The patent shifts the isolation approach from a distributed two-dimensional pattern between fingers to a concentrated peripheral arrangement. By moving isolation structures to the edges and utilizing the peripheral dimension more effectively, more active region can be integrated in the available space without compromising isolation.
Data Source
AI summary
A lateral double diffused metal oxide semiconductor (LDMOS) transistor and a semiconductor can reduce the size of the entire power block and can decrease costs by preventing formation of an edge termination region between adjacent device tips or ends along a width direction when the corresponding LDMOS transistor cell has a limited width and the LDMOS transistor is a multi-finger LDMOS transistor.