LDMOS Edge Termination Structure for Snapback SOA Improvement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
LDMOS transistors face issues with inductively induced high di/dt causing parasitic bipolar transistor action, leading to non-uniform voltage breakdown and reduced safe operating area (SOA) due to parasitic bipolar transistor triggering.
Innovation Solution
The LDMOS transistor design includes a well region that laterally encircles the finger structure, with a deep trench isolation structure and a buried layer, along with a metallization structure connecting the source fingers to the well and buried layer, enhancing snapback current capability and breakdown voltage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then device simplicity is maintained, but parasitic bipolar transistor triggering occurs due to inductively induced high di/dt, reducing safe operating area
Solution Approach 1:
The device structure is segmented into multiple functional regions including a drift region, a first well region, a second well region, and a third well region. These segmented regions work together to control electric field distribution and prevent parasitic bipolar transistor triggering, thereby improving safe operating area while managing device complexity through functional decomposition
Solution Approach 2:
Different regions of the transistor are doped with different doping types and concentrations to create local quality variations. The drift region has one doping characteristic while the well regions have different doping characteristics, allowing each region to perform its specific function optimally - the drift region for voltage blocking and the well regions for preventing parasitic activation
2Reliability
If conventional edge termination is used, then manufacturing simplicity is maintained, but non-uniform voltage breakdown occurs at the device edge, limiting reverse bias snap back current capability
Solution Approach 1:
The edge termination structure extends the well regions in multiple spatial dimensions - the second well region laterally extends around and encircles the finger structure, while the third well region is positioned at specific depths. This multi-dimensional arrangement ensures uniform voltage breakdown at the device edge by distributing the electric field evenly across the termination region
3Reliability
If source potential is allowed to rise with high di/dt, then inductive effects are accepted, but parasitic bipolar transistor action is triggered even with grounded source and buried layer
Solution Approach 1:
The well regions are positioned and doped to create preliminary anti-action against the parasitic bipolar transistor effect. The second well region encircling the finger structure and the third well region at specific depths create opposing electric field effects that counteract the inductively induced di/dt before it can trigger parasitic bipolar transistor action
Solution Approach 2:
The well regions act as intermediary structures between the source and the parasitic bipolar transistor base region. These intermediary well regions with specific doping characteristics modify the electric field distribution to prevent the direct interaction that would otherwise trigger parasitic bipolar transistor action during high di/dt events
Data Source
AI summary
An electronic device includes a semiconductor layer with majority carriers of a first dopant type, a transistor finger structure extending along a first direction and including a drain finger and source fingers having majority carriers of a second type and laterally spaced apart from opposite sides of the drain finger along the second direction and a well region including majority carrier dopants of the first type in the semiconductor layer, the source fingers extending in respective portions of the well region, and the well region laterally extending around and encircling the finger structure.