LDMOS Electrode Pillar Structure for Smaller Lateral Footprint
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Solution Overview
Problem
Laterally-diffused metal-oxide-semiconductor (LDMOS) devices occupy a large area in integrated circuits due to their horizontal extension, which hinders integrated circuit density improvements.
Innovation Solution
The semiconductor device employs a structure with conductive pillars to lead out electrodes without a drain doped region, reducing the lateral size by omitting the drain doped region and using a parallel connection of first and second conductive pillars with specific thicknesses of titanium and titanium nitride layers to ensure effective ohmic contact and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional LDMOS device structure with drain doped region is used, then good electrical contact and current flow are achieved, but the lateral area occupied is large
Solution Approach 1:
The patent extracts and removes the drain doped region from the conventional LDMOS structure. By eliminating this region and using two separate conductive pillars to contact the drift region directly, the lateral area is reduced while maintaining electrical functionality through alternative contact paths.
Solution Approach 2:
The drain electrode is segmented into two separate conductive pillars instead of a single continuous drain doped region. This segmentation allows the electrode to contact the drift region at multiple discrete points, reducing the lateral footprint while ensuring reliable electrical connection through distributed contact points.
2Productivity
If the lateral size of LDMOS device is reduced, then integrated circuit density is improved, but electrical performance may be compromised
Solution Approach 1:
The patent transitions from a planar contact structure to a vertical stacked structure. The two conductive pillars extend vertically to contact the drift region, utilizing the vertical dimension to achieve electrical connection without increasing lateral footprint, thereby maintaining circuit density while ensuring electrical performance.
Solution Approach 2:
The patent employs a composite structure combining interlayer dielectric materials with specific metal materials for the conductive pillars. This composite approach allows optimization of each material's properties - the dielectric provides isolation and mechanical support while the metal pillars provide low-resistance electrical contact, achieving both density and performance goals.
Data Source
AI summary
A semiconductor device can include: a semiconductor doped region; a patterned interlayer dielectric layer located on the semiconductor doped region; an electrode structure connected to the semiconductor doped region through opening holes of the interlayer dielectric layer; a patterned metal silicide layer located on the semiconductor doped region; where the electrode structure comprises a first conductive pillar and a second conductive pillar, the first conductive pillar is connected to the metal silicide layer, and the second conductive pillar is connected to an upper surface of the semiconductor doped region; and where the first conductive pillar and the second conductive pillar are not in contact with a heavily doped region in the semiconductor doped region, and the doping concentration of the semiconductor doped region is not greater than 1018 cm−3.