LDMOS Transistor Elevated Field Oxide Bumps Low On-Resistance
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Solution Overview
Problem
Conventional LDMOS transistors exhibit high on-resistance and hot carrier degradation due to thick field oxide regions, which impede current flow and reduce breakdown voltage, while shallow trench isolation increases on-resistance and sharp corners exacerbate hot carrier degradation.
Innovation Solution
An LDMOS transistor with an elevated thick gate dielectric region is fabricated using a shallow field oxide formation process, where a hard mask exposes the substrate region for thermal oxidation, followed by chemical mechanical polishing to create a shallow field oxide and gate dielectric combination that minimizes the current path impedance and maintains robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick field oxide regions are used to provide electrical isolation and protect gate oxide, then breakdown voltage is improved, but on-resistance increases due to long current path under the oxide
Solution Approach 1:
The patent transitions from a planar field oxide structure to a three-dimensional elevated gate dielectric structure. The gate dielectric is raised above the substrate surface, creating vertical stacking that separates the gate electrode from the drain region while minimizing the horizontal current path length, thus reducing on-resistance while maintaining breakdown voltage protection
Solution Approach 2:
The gate dielectric structure is segmented into multiple layers including the shallow field oxide region, the elevated gate dielectric layer, and the gate electrode. This segmentation allows each layer to perform its specific function: the shallow oxide provides isolation, the elevated dielectric provides electrical protection with minimal current path interference, and the gate electrode controls the channel
2Reliability
If shallow trench isolation is used to reduce field oxide depth, then on-resistance is reduced, but sharp corners at trench edges increase electric field concentration causing hot carrier degradation
Solution Approach 1:
The patent replaces the sharp-cornered trench isolation with a curved, elevated gate dielectric structure. The rounded top surface of the elevated gate dielectric eliminates sharp corners that would concentrate electric fields, thereby preventing hot carrier degradation while maintaining the reduced current path length benefit
Solution Approach 2:
The gate dielectric structure has non-uniform thickness with a shallower depth at the edges and a raised center region. This local variation in geometry allows the edges to have reduced electric field concentration while the center provides adequate electrical isolation and protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resulting LDMOS transistor achieves a 30% reduction in on-resistance and significantly improved robustness against hot carrier degradation with comparable or better breakdown and threshold voltages compared to conventional transistors, while maintaining a compact layout area compatible with deep sub-micron VLSI processes.
Implementation Method 1
performing a thermal oxidation step through the opening of this mask, thereby forming a shallow field oxide region
Implementation Method 2
followed by chemical mechanical polishing to create a shallow field oxide and gate dielectric combination
Data Source
AI summary
A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance.