LDMOS Bulk Substrate Isolation Using Embedded Layer and Deep Trench
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Solution Overview
Problem
LDMOS transistors exhibit poor substrate isolation, leading to reduced breakdown voltages, which is partially addressed by using silicon on insulator (SOI) technology but at the cost of expensive wafer implementation.
Innovation Solution
A bulk semiconductor substrate with an embedded isolation layer and dual depth isolation structures, including a deep trench and shallow trench isolation, to define an active area for the gate structure, improving device performance without the high cost of SOI wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI technology is used to improve substrate isolation, then breakdown voltage is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies local quality by embedding an isolation layer only in specific regions where substrate isolation is needed, rather than using a complete SOI structure. The isolation layer is positioned locally beneath the active area to provide targeted substrate isolation improvement while avoiding the high cost of full SOI wafers.
Solution Approach 2:
The patent implements nesting by placing an isolation layer within the bulk substrate, creating a nested structure where the isolation layer is embedded inside the substrate. This nested approach allows substrate isolation functionality to be integrated within the bulk substrate itself, eliminating the need for expensive SOI wafers while maintaining the isolation effect.
2Ease of manufacture
If LDMOS is fabricated on bulk substrate, then manufacturing cost is reduced, but substrate isolation deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the isolation layer within the bulk substrate before fabricating the LDMOS device. This pre-established isolation layer provides substrate isolation improvement from the outset, allowing subsequent LDMOS fabrication to proceed on a bulk substrate with enhanced isolation characteristics, thus maintaining cost-effectiveness while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded isolation layer enhances device performance by improving substrate isolation, increasing breakdown voltages, and reducing parasitic bipolar issues, while maintaining cost-effectiveness compared to SOI technologies.
Implementation Method 1
an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate
Implementation Method 2
a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.