LDMOS ESD Clamp with Layout-Configurable Trigger Voltage
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Solution Overview
Problem
Existing ESD protection circuits with silicon-controlled rectifier (SCR) structures often experience low snapback holding voltage, which is insufficient for protecting integrated circuits with high operational voltages, leading to potential damage during ESD events due to false-triggering and latch-on issues.
Innovation Solution
The design incorporates a lateral diffused metal-oxide semiconductor (LDMOS) transistor with a drain contact region laterally displaced from the channel, allowing for higher trigger and holding voltages, and eliminating the need for an SCR structure to prevent snapback, thus providing robust ESD protection for high-voltage circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the holding voltage is lower than the supply voltage, then the ESD device provides effective discharge path during ESD events, but the device remains in latched-on state during normal operation causing permanent damage
Solution Approach 1:
The patent elevates the holding voltage parameter above the supply voltage by using a DEMOS transistor with appropriate doping profiles and geometric configurations. This ensures the transistor remains in high-impedance state during normal operation and only activates during genuine ESD events, maintaining both discharge capability and device reliability.
2Reliability
If a DEMOS transistor is used instead of SCR, then the trigger voltage and holding voltage can be higher than supply voltage, but the device complexity increases
Solution Approach 1:
The DEMOS transistor serves multiple functions: it provides ESD protection, maintains high-impedance state during normal operation, and eliminates the need for separate SCR structures. This multi-functionality achieves reliable ESD protection with higher voltage thresholds while managing device complexity through consolidation of protection mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The LDMOS transistor configuration ensures the ESD device remains in a high-impedance state during normal operation and effectively turns on during ESD events, providing a low-impedance discharge path without snapback, effectively protecting high-voltage circuits from damage and maintaining functionality after multiple ESD zaps.
Implementation Method 1
effectively turns on during ESD events, providing a low-impedance discharge path
Implementation Method 2
remains in a high-impedance state during normal operation
Data Source
AI summary
An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.