LDMOS ESD Protection via Heavily Doped Substrate Region
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Solution Overview
Problem
Conventional LDMOS transistors in integrated circuits are vulnerable to high-voltage electrostatic discharge (ESD) due to energy distribution towards the gate oxide layer, leading to breakdown, and existing ESD protection components increase complexity and cost.
Innovation Solution
The introduction of a lateral diffused metal oxide semiconductor (LDMOS) device structure with an additional heavily doped region between the semiconductor substrate and epi-layer, which redirects ESD current towards the substrate, reducing breakdown voltage and punch-through voltage, thereby enhancing ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then device simplicity and low manufacturing cost are maintained, but ESD protection capability deteriorates due to gate oxide breakdown
Solution Approach 1:
The invention merges the LDMOS transistor structure with ESD protection functionality by adding a heavily doped region between the drain and substrate. This integration allows the transistor to inherently protect against ESD events without requiring separate protection components, thus improving reliability while maintaining structural simplicity.
Solution Approach 2:
The heavily doped region acts as an intermediary between the drain and substrate, providing a preferred conduction path for ESD current. This intermediary structure redirects the harmful ESD energy away from the gate oxide, preventing breakdown while maintaining the original transistor's operational characteristics.
2Reliability
If additional ESD protection components are added, then ESD protection capability is improved, but occupied space and fabrication complexity increase
Solution Approach 1:
The invention combines ESD protection functionality within the existing LDMOS transistor footprint by modifying the transistor's internal structure. The heavily doped region is integrated into the drain extension area, eliminating the need for separate ESD protection components and thereby reducing occupied space while maintaining protection capability.
3Reliability
If additional ESD protection components are added, then ESD protection capability is improved, but manufacturing cost increases
Solution Approach 1:
The invention integrates ESD protection functionality into the existing LDMOS fabrication process by adding a heavily doped region that can be formed using standard ion implantation or diffusion techniques. This approach eliminates the need for additional fabrication steps or specialized processes, thereby reducing manufacturing cost while achieving ESD protection.
4Productivity
If gate oxide layer is positioned close to drain region, then transistor performance is improved, but vulnerability to ESD damage increases
Solution Approach 1:
The heavily doped region serves as a mediator between the drain and substrate, creating a low-resistance path for ESD current. This intermediary structure protects the gate oxide from direct exposure to ESD energy while maintaining the close positioning of the gate oxide to the drain for optimal transistor performance.
Solution Approach 2:
The invention converts the potentially harmful ESD energy into a beneficial protective mechanism. The heavily doped region is designed to break down at a lower voltage than the gate oxide, allowing controlled breakdown that dissipates ESD energy safely through the substrate, thereby protecting the more critical gate oxide structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively distributes electrostatic charge to the semiconductor substrate instead of the gate oxide layer, preventing damage and simplifying fabrication while reducing manufacturing costs.
Implementation Method 1
LDMOS transistors are vulnerable to high-voltage (HV) electrostatic discharge damage... when the ESD current travels from the drain end of the transistor, the energy of the ESD current tends to distribute towards the gate oxide layer
Implementation Method 2
an additional heavily doped region is formed between the semiconductor substrate and the epi-layer... reduces breakdown voltage and punch-through voltage, thereby enhancing ESD protection
Data Source
AI summary
Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+ doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+ doped source region and a P+ diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+ doped source region and the N+ doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer. The punch-through voltage or the breakdown voltage of the interface can be adapted by regulating the P+ or N+ dosage to exceed the breakdown voltage of the LDNMOS transistor or the LDPMOS transistor. It can be able to effectively reduce the breakdown voltage or the punch-through voltage relative to the semiconductor substrate under the drain region, thus increasing ESD protection.