LDMOS Transistor ESD Tolerance via Segmented Source Layer
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Solution Overview
Problem
LDMOS transistors face issues with parasitic NPN transistor activation due to high energy electrons and holes generated during ESD events, leading to increased unnecessary current and potential thermal runaway, which compromises ESD tolerance and device reliability.
Innovation Solution
The design includes a semiconductor transistor with a source layer featuring a plurality of openings and a P+ type contact layer buried within these openings, increasing the distance between the contact layer edge and the source layer edge to enhance ESD tolerance by allowing broader parasitic NPN transistor activation and improved current handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the P+ type contact layer is formed close to the N+ type source layer edge, then the device area is reduced and manufacturing is simplified, but the ESD tolerance decreases due to localized current convergence causing thermal runaway
Solution Approach 1:
The N+ type source layer is divided into multiple regions separated by gaps, with P+ type contact layers formed in each gap region. This segmentation distributes the ESD current across multiple discharge paths rather than concentrating it in one location, preventing thermal runaway while maintaining compact device area.
Solution Approach 2:
The P+ type contact layer is strategically positioned in specific gap regions between N+ type source layer portions, creating localized high-conductivity paths. This local quality enhancement allows ESD current to be diverted at specific locations without requiring the contact layer to be uniformly distributed, optimizing both ESD tolerance and area efficiency.
2Reliability
If the distance between contact layer edge and source layer edge is increased, then ESD tolerance is improved by allowing broader parasitic NPN transistor activation, but the device area increases
Solution Approach 1:
The gap width between N+ type source layer portions is dynamically optimized to a specific range (0.5-2.0 μm) that allows sufficient parasitic NPN transistor activation for ESD protection while minimizing area consumption. This dynamic parameter optimization balances ESD tolerance requirements with area efficiency.
Solution Approach 2:
The critical parameter is the gap width between N+ type source layer portions, which is changed from a fixed small value to an optimized range (0.5-2.0 μm). This parameter change enables broader parasitic NPN transistor activation for improved ESD tolerance while controlling area increase through precise dimensional control.
3Reliability
If the P+ type contact layer is positioned to maximize ESD tolerance, then HBM+ESD tolerance reaches saturation at optimal distance, but further increases in distance provide diminishing returns
Solution Approach 1:
The gap width is set to a value (0.5-2.0 μm) that provides sufficient separation for parasitic NPN transistor activation to occur, achieving near-maximum ESD tolerance. Going beyond this range provides diminishing returns, so the design uses partial action (just enough separation) rather than excessive separation, balancing ESD tolerance with structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the HBM+ESD tolerance of the LDMOS transistor by allowing the parasitic NPN transistor to be activated over a broader area, effectively managing surge currents and preventing thermal runaway, thereby enhancing the device's ESD tolerance and reliability.
Implementation Method 1
electrons accelerated in the N− type drift layer 52 are turned into hot electrons having high energy, and interact with lattices and the like in the N− type drift layer 52 to generate a large number of electron-hole pairs
Implementation Method 2
When the LDMOS transistor is turned on, electrons flow out of the N+ type source layer 56 into the N− type drift layer 52 through a channel layer, are accelerated by a high electric field in the N− type drift layer 52
Implementation Method 3
the parasitic NPN transistor, which is composed of an emitter made of the N+ type source layer 56, a base made of the P type base layer 53 and a collector made of the N+ type drain layer 57, is turned on and the electron current flows out of the N+ type source layer 56 to the P type base layer 53
Data Source
AI summary
An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.