LDMOS ESD Protection Trigger Voltage Reduction
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Solution Overview
Problem
Conventional lateral double diffused metal oxide semiconductor (LDMOS) devices for electrostatic discharge (ESD) protection circuits are ineffective as they are triggered later than the internal high voltage devices they are meant to protect, due to a floating gate electrode during ESD events, rendering them useless in protecting the output driver.
Innovation Solution
The LDMOS device design includes a substrate, deep well region, body region, doped regions, and a gate electrode with an isolation structure and drift region, where the body region lacks a doped region of different conductivity type, forming a Shottky contact with higher resistance, allowing the parasitic bipolar junction transistor to turn on quickly and reduce the trigger voltage, enabling faster activation during ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-grounded LDNMOS device is used as an ESD protection device for high voltage output drivers, then the output driver can be protected against ESD damage, but the gate electrode of the output driver is floating under ESD transient condition causing the trigger voltage of the output driver to be equal to or less than that of the ESD protection device, making the ESD protection device useless
Solution Approach 1:
The patent changes the doping concentration parameters in the body region and deep well region to create a parasitic bipolar transistor with lower trigger voltage. By adjusting the doping concentrations (e.g., body region doping of 1E16 to 1E18 atoms/cm³ and deep well region doping of 1E18 to 1E20 atoms/cm³), the parasitic BJT turns on faster than the main LDMOS device during ESD events, resolving the contradiction between protection effectiveness and turn-on speed.
Solution Approach 2:
The patent introduces a parasitic bipolar junction transistor as an intermediary mechanism between the ESD protection device and the output driver. This parasitic BJT acts as a mediator that activates first during ESD transients to clamp the voltage before the main LDMOS device turns on, effectively solving the timing issue where the protection device would otherwise turn on too slowly.
2Speed
If the trigger voltage of the ESD protection device is reduced to enable faster turn-on, then the ESD protection device can activate more quickly, but the holding voltage may also decrease reducing the protection capability
Solution Approach 1:
The patent segments the ESD protection mechanism into two distinct stages: a fast-acting parasitic BJT stage that provides immediate voltage clamping at lower voltage, and a main LDMOS device stage that provides sustained protection at higher holding voltage. This segmentation allows the system to achieve both fast turn-on (via parasitic BJT) and high holding voltage (via main LDMOS) without compromise.
Solution Approach 2:
The parasitic bipolar transistor performs preliminary action by activating first during ESD transients to quickly clamp the voltage and protect sensitive nodes. This preliminary protection occurs before the main LDMOS device fully turns on, enabling the system to achieve fast initial response while maintaining the higher holding voltage capability of the main device for sustained protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The LDMOS device can be turned on more quickly than conventional devices, reducing the trigger voltage and enhancing ESD protection capabilities with a lower holding voltage and higher second breakdown current, thus effectively safeguarding internal devices from ESD damage.
Implementation Method 1
a junction between the contact and the body region is a Shottky contact
Data Source
AI summary
A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region.