Segmented LDMOS Field Plates to Balance Breakdown and On-Resistance
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Solution Overview
Problem
Conventional shallow trench isolation (STI) technology used in LDMOS devices increases breakdown voltage but compromises on-resistance performance.
Innovation Solution
The method involves forming an LDMOS device with a semiconductor substrate having a drift region and a body region, where a barrier layer with n etch stop layers and insulating layers is deposited, and field plate holes are etched to form field plates on the etch stop layers, eliminating the need for STI around the drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If shallow trench isolation (STI) technology is used to increase breakdown voltage, then breakdown voltage is improved, but on-resistance increases
Solution Approach 1:
The patent divides the field plate structure into multiple segments by introducing multiple etch stop layers (first etch stop layer, second etch stop layer, etc.) at different depths within the drift region. Each etch stop layer can be independently etched to form separate field plate holes, allowing the field plate to be segmented into multiple sections. This segmentation enables precise control of the electric field distribution at different locations, increasing breakdown voltage without creating the high on-resistance associated with conventional STI structures.
Solution Approach 2:
The patent applies different properties to different parts of the drift region by placing etch stop layers and field plates at specific locations. The first etch stop layer is positioned closer to the gate structure while the second etch stop layer is positioned deeper in the drift region. This local differentiation allows the electric field to be controlled locally at critical breakdown points without affecting the overall conductivity of the drift region, thus improving breakdown voltage while maintaining low on-resistance.
2Strength
If multiple etch stop layers are introduced to control electric field distribution, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The patent combines the formation of multiple field plate holes with a single etching process. By designing the etch stop layers with different etching resistances or depths, the etching process automatically stops at different levels to create multiple field plate holes in one step. This merging of operations reduces the number of separate fabrication steps compared to forming each field plate hole individually, thereby managing device complexity while achieving improved breakdown voltage control.
Solution Approach 2:
The etch stop layers are pre-formed within the drift region before the field plate holes are created. This preliminary action of depositing and patterning the etch stop layers establishes a template that guides subsequent etching operations. By preparing this structural framework in advance, the patent simplifies the overall fabrication process and reduces the complexity of real-time process control during field plate formation.
Data Source
AI summary
The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.