LDMOS Transistor with Extrinsic Breakdown Region
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Solution Overview
Problem
Conventional LDMOS transistors experience breakdown at a high-resistance region, leading to device degradation and reliability issues due to impact ionization, which is exacerbated by attempts to minimize this region for improved performance.
Innovation Solution
The design incorporates a breakdown region outside the channel with an extrinsic breakdown voltage lower than the intrinsic breakdown voltage, allowing electron-hole pairs generated by impact ionization to occur away from the intrinsic channel region, thereby preventing FET on-resistance degradation without increasing silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the high-resistance region is minimized to improve device performance, then the on-resistance is reduced, but the electrical field gradient increases causing higher impact ionization rate and device breakdown
Solution Approach 1:
The patent extracts the breakdown-prone high-resistance region from the main current channel by creating a separate breakdown region adjacent to the channel. This allows the channel to be optimized for low on-resistance while the extracted breakdown region handles the impact ionization events, preventing device degradation.
Solution Approach 2:
The patent introduces an intermediary breakdown region that acts as a mediator between the high-current channel and the substrate. This intermediary region absorbs the harmful impact ionization effects through controlled avalanche breakdown, protecting the main channel from degradation while allowing the channel to maintain low resistance.
2Reliability
If a second device with lower breakdown voltage is added in parallel to clamp drain voltage, then device breakdown is prevented, but system complexity and component count increase
Solution Approach 1:
The patent merges the breakdown protection function directly into the transistor structure by integrating a breakdown region within the same device. This combines what would traditionally require separate protection devices into a single unified structure, reducing system complexity and component count while maintaining breakdown protection.
Solution Approach 2:
The patent enables the transistor to provide its own breakdown protection through the integrated breakdown region. The device becomes self-protecting by clamping its own drain voltage through internal avalanche breakdown, eliminating the need for external protection circuits or additional devices.
3Reliability
If breakdown region is created outside the channel, then FET on-resistance degradation is prevented, but breakdown voltage is slightly reduced
Solution Approach 1:
The patent applies local quality by creating a breakdown region with specific doping characteristics adjacent to the channel. This localized region has optimized properties for handling breakdown events, allowing the main channel to maintain low resistance while the local breakdown region provides protection with only minimal impact on overall breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents avalanche breakdown-induced FET on-resistance degradation while maintaining a slight reduction in breakdown voltage, achieving self-protection without significant silicon area sacrifice.
Implementation Method 1
electron-hole pairs generated by impact ionization
Data Source
AI summary
A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.