LDMOS False Drain Emulates Low Voltage Reliability
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Solution Overview
Problem
The development of laterally diffused metal-oxide-semiconductor (LDMOS) devices capable of operating at higher voltages is resource-intensive and time-consuming due to the need for extensive reliability testing for hot carrier injection (HCI) and gate oxide (GOX) effects, which hinders the rapid integration of these devices into production.
Innovation Solution
Incorporating a false drain adjacent to the channel region in LDMOS devices, allowing them to emulate a lower voltage transistor design, thereby reusing existing reliability data and reducing the need for additional HCI and GOX testing, and utilizing shared fabrication procedures with lower voltage tier devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive reliability testing is performed for hot carrier injection and gate oxide effects, then device reliability is improved, but development time and resources increase significantly
Solution Approach 1:
The patent applies preliminary action by designing the LDMOS device structure in advance to inherently satisfy reliability requirements. The drift space geometry and doping profile are predetermined to limit hot carrier injection and gate oxide stress, allowing the device to pass reliability tests by design rather than requiring extensive post-fabrication testing and iteration.
Solution Approach 2:
The patent uses parameter changes by optimizing the drift space dimensions and doping concentration to achieve reliable operation. Specific parameters such as drift space width, doping profile, and junction depths are carefully controlled to create electric field distributions that prevent harmful hot carrier effects, thereby ensuring reliability without requiring multiple design iterations and extensive testing.
2Reliability
If extensive reliability testing is performed for hot carrier injection and gate oxide effects, then device reliability is improved, but manufacturing resources and costs increase
Solution Approach 1:
The patent applies preliminary action by designing the LDMOS device structure in advance to inherently satisfy reliability requirements. The drift space geometry and doping profile are predetermined to limit hot carrier injection and gate oxide stress, allowing the device to pass reliability tests by design rather than requiring extensive post-fabrication testing and iteration.
Solution Approach 2:
The patent uses parameter changes by optimizing the drift space dimensions and doping concentration to achieve reliable operation. Specific parameters such as drift space width, doping profile, and junction depths are carefully controlled to create electric field distributions that prevent harmful hot carrier effects, thereby ensuring reliability without requiring multiple design iterations and extensive testing.
3Power
If higher operating voltages are implemented in LDMOS devices, then device performance is improved, but off-state breakdown voltage control becomes more difficult
Solution Approach 1:
The patent uses parameter changes by optimizing the drift space dimensions and doping concentration to achieve reliable operation. Specific parameters such as drift space width, doping profile, and junction depths are carefully controlled to create electric field distributions that prevent harmful hot carrier effects, thereby ensuring reliability without requiring multiple design iterations and extensive testing.
Solution Approach 2:
The patent applies feedback by using simulation and modeling during the design phase to predict breakdown voltage characteristics. The drift space parameters are iteratively optimized based on simulated electric field distributions and breakdown behavior, allowing precise control of breakdown voltage before fabrication. This virtual feedback loop enables accurate prediction and adjustment of breakdown characteristics without requiring extensive physical prototyping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach accelerates the development and integration of higher voltage LDMOS devices by leveraging existing reliability data, reducing development time and resources, while maintaining or improving off-state breakdown voltage levels.
Implementation Method 1
The RESURF structure is designed to deplete the drift space in the LDMOS device in both vertical and lateral directions, thereby reducing the electric field near the surface at the drift region
Implementation Method 2
The RESURF structure is designed to deplete the drift space in the LDMOS device in both vertical and lateral directions, thereby reducing the electric field near the surface at the drift region and thus raising the off-state breakdown voltage (BVDSS) of the device
Data Source
AI summary
An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.