LDMOS on FDSOI with Segmented Gate Oxide for High Voltage
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Solution Overview
Problem
Current fully depleted silicon on insulator (FDSOI) technology cannot support high gate-source (Vgs) voltages required for high voltage applications, limiting the functionality of LDMOS devices in power ICs, especially for automotive electronics and MEMS, as they typically allow only up to 1.8V Vgs.
Innovation Solution
The implementation of a laterally double diffused semiconductor device with a buried oxide layer as a gate dielectric and a semiconductor on insulator material as a channel region, along with source/drain regions, enables the use of a back-gate voltage to control the channel and drift region, allowing for high Vgs voltages of 15V or greater while maintaining low switching times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate oxide is used to support high Vgs voltage, then the voltage rating is improved, but the switching time increases and device performance deteriorates
Solution Approach 1:
The gate oxide is segmented into two distinct layers: a thin first gate oxide layer (5-15 nm) close to the silicon surface that enables fast switching, and a thick second gate oxide layer (50-200 nm) that provides high voltage rating. This segmentation allows each layer to perform its specific function optimally without compromising the other.
Solution Approach 2:
The patent introduces a vertical dimension to the gate oxide structure by stacking two oxide layers with different thicknesses. This dimensional approach allows the device to simultaneously achieve properties that would be contradictory in a single-layer structure: fast switching (from the thin layer) and high voltage tolerance (from the thick layer).
2Ease of manufacture
If current FDSOI technology is used, then manufacturing compatibility is maintained, but high Vgs voltage capability cannot be achieved
Solution Approach 1:
The dual-layer gate oxide structure serves multiple functions: the thin first layer maintains compatibility with standard FDSOI manufacturing processes and enables fast switching, while the thick second layer provides high voltage rating capability. This multi-functional design allows a single device structure to meet both manufacturing constraints and performance requirements.
Solution Approach 2:
The patent changes the physical parameters of the gate oxide by introducing a second layer with different thickness characteristics. This parameter modification allows the device to operate in a new regime where both low-voltage compatibility and high-voltage capability coexist, expanding the operational range of FDSOI technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows LDMOS devices to sustain high input voltages and achieve low switching times, addressing the limitations of existing FDSOI technology by reducing gate-related parasitics and enabling high Vgs voltages, essential for advanced power IC applications.
Implementation Method 1
A gate terminal is placed at a hybrid section is used as a back-gate voltage to control the channel and the drift region of the transistor
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.