LDMOS Field Drain Section for Breakdown Voltage Improvement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The breakdown voltage of LDMOS transistors is limited due to impact ionization at the boundary between the field drain section and the semiconductor substrate, which saturates the improvement of drain-to-substrate breakdown voltage.
Innovation Solution
A field drain section is formed with a structure comprising a first insulating film in contact with the semiconductor substrate and a second insulating film with a higher dielectric constant, positioned between the gate electrode and the drain diffusion region, to relax electric field concentration and suppress impact ionization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field drain section is formed using the same process as STI structure, then the drain-to-substrate breakdown voltage is improved, but impact ionization occurs at the boundary between the field drain section and semiconductor substrate, causing breakdown voltage improvement to be saturated
Solution Approach 1:
The patent applies local quality by forming a field drain section with spatially varying dielectric constant - higher near the semiconductor substrate boundary and lower toward the gate electrode. This gradient structure locally optimizes the electric field distribution at the critical boundary region, suppressing impact ionization where it occurs most while maintaining overall breakdown voltage improvement.
Solution Approach 2:
The patent changes the dielectric constant parameter of the insulating film within the field drain section, creating a gradient from higher dielectric constant near the substrate to lower dielectric constant near the gate. This parameter variation optimizes electric field distribution and suppresses impact ionization at the boundary region.
2Reliability
If the field drain section uses a thick insulating film to improve breakdown voltage, then the drain-to-substrate breakdown voltage increases, but parasitic capacitance increases, affecting circuit operation speed
Solution Approach 1:
The patent uses local quality by positioning the high dielectric constant region specifically where it provides maximum benefit (near the substrate boundary for breakdown voltage) while keeping the upper region with lower dielectric constant to minimize parasitic capacitance. This spatial differentiation resolves the contradiction between reliability and speed.
Solution Approach 2:
The patent employs composite materials with different dielectric constants in a vertically stacked configuration within the field drain section. The lower layer has higher dielectric constant for breakdown voltage enhancement, while the upper layer has lower dielectric constant to minimize parasitic capacitance, achieving both reliability and speed requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the drain-to-substrate breakdown voltage without saturation, enhances long-term reliability by reducing crystal defects, and maintains circuit operation speed by minimizing parasitic capacitance.
Implementation Method 1
a second insulating film configured to be formed on the first insulating film and has a dielectric constant higher than a dielectric constant of the first insulating film
Implementation Method 2
impact ionization is apt to be generated at a boundary between the field drain section and the semiconductor substrate. The impact ionization implies a phenomenon in which many electron-hole pairs are generated by collisions between crystal lattices and electrons accelerated by an electric field
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; a source diffusion layer and a drain diffusion layer formed on both sides of the gate electrode, respectively, in the semiconductor substrate; and a field drain section formed below the gate electrode in the semiconductor substrate so as to be positioned between the gate electrode and the drain diffusion region and include an insulator. The field drain section includes: a first insulating film configured to be contact with the semiconductor substrate, and a second insulating film configured to be formed on the first insulating film and has a dielectric constant higher than a dielectric constant of the first insulating film.