LDMOS Field Plate Layout for Avalanche Current Suppression
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Solution Overview
Problem
Conventional high breakdown voltage LDMOS transistors exhibit increased current as source-drain voltage increases without saturation in the on state, leading to reliability issues and potential element destruction in drive circuits, particularly when transitioning through the avalanche region.
Innovation Solution
The transistor design includes a body region of a first conductivity type, source and drain regions of a second conductivity type, a gate electrode, first and second field plates, and buried regions with specific impurity concentrations and distances to ensure uniform electric potential distribution and suppress electric field concentration, thereby reducing current dependence on source-drain voltage in the saturation region and increasing the voltage at which rapid current increase begins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the impurity concentration of the drift region is increased to reduce on-resistance, then the on-resistance decreases, but the breakdown voltage decreases and the transistor cannot achieve high breakdown voltage of 100V or higher
Solution Approach 1:
The drift region is divided into multiple segments with different impurity concentrations: a first drift region with higher impurity concentration (5×10^15 to 5×10^16/cm³) adjacent to the body region, and a second drift region with lower impurity concentration (1×10^15 to 5×10^15/cm³) adjacent to the drain region. This segmentation allows the first drift region to provide low on-resistance while the second drift region provides high breakdown voltage, resolving the contradiction between low on-resistance and high breakdown voltage.
2Use of energy by moving object
If a single high-concentration buried layer is used to reduce on-resistance, then the on-resistance decreases, but the electric field concentrates at the drain junction causing early avalanche breakdown
Solution Approach 1:
The patent employs a dual-buried-layer structure with different local properties: a first buried layer with higher impurity concentration (1×10^18 to 1×10^19/cm³) positioned adjacent to the body region to reduce on-resistance, and a second buried layer with lower impurity concentration (1×10^17 to 1×10^18/cm³) positioned adjacent to the drain region to suppress electric field concentration. This local quality differentiation allows each buried layer to perform its specific function, resolving the contradiction between low on-resistance and high avalanche breakdown voltage.
3Strength
If the drift region length is increased to increase breakdown voltage, then the breakdown voltage increases, but the on-resistance increases and the transistor cannot achieve low on-resistance
Solution Approach 1:
The drift region is designed with spatially varying impurity concentration: the first drift region adjacent to the body region has higher impurity concentration (5×10^15 to 5×10^16/cm³) to reduce on-resistance, while the second drift region adjacent to the drain region has lower impurity concentration (1×10^15 to 5×10^15/cm³) to increase breakdown voltage. This allows the drift region to simultaneously achieve low on-resistance and high breakdown voltage without increasing the overall drift region length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a high breakdown voltage with low on-resistance, reduces current dependence on source-drain voltage in the saturation region, and enhances reliability by suppressing avalanche current and maintaining consistent transistor characteristics over time.
Implementation Method 1
a gate electrode controlling a current between the source region and the drain region via a body region
Implementation Method 2
controlling a current between the source region and the drain region
Implementation Method 3
suppress electric field concentration, thereby reducing current dependence on source-drain voltage
Implementation Method 4
suppressing avalanche current and maintaining consistent transistor characteristics
Data Source
Figure 1
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Figure 3
AI summary
An LDMOS transistor includes a P-type body region (6) on a main surface of a semiconductor substrate (1), an N-type source region (9), an N-type drift region (7), an N-type drain region (10), a gate electrode (13) formed via a gate insulating film (12), a first field plate (13) formed on the drift region via a first insulating film (8), second field plates (16a, 19a) contacting the source region or gate electrode and formed on the first field plate via a second insulating film (14), a P-type first buried region (4), and a P-type second buried region (5) having a lower impurity concentration than the first buried region. Distances of the first and second field plates from the drain region in the semiconductor substrate plane direction decrease toward upper layers, and have a predetermined relationship with distances (LB 1, LB2) between the first and second buried regions and the drain region.