LDMOS Field Plate Structure for Hot Carrier and Breakdown Control
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Solution Overview
Problem
Existing power metal-oxide-semiconductor field-effect transistors (MOSFETs), particularly laterally-diffused metal-oxide semiconductor (LDMOS) transistors, face challenges in managing high electric fields, which can lead to hot carrier effects and reduced breakdown voltages.
Innovation Solution
The development of a p-type LDMOS (PLDMOS) device with a field plate adapted to distribute the electric field more evenly, reducing its peak value on the drain side, integrated into a smart power integrated circuit using a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional LDMOS transistor structure is used, then high power output is achieved, but peak electric field concentration occurs leading to hot carrier effects and reduced breakdown voltage
Solution Approach 1:
A field plate electrode is introduced as an intermediary structure between the drain electrode and the gate electrode. This field plate distributes the electric field more evenly across the drain region, reducing peak electric field concentration that causes hot carrier effects. The field plate acts as a mediator that modifies the electric field distribution without directly interfering with the high power output function of the conventional LDMOS structure.
Solution Approach 2:
The field plate extends in the lateral dimension beyond the gate electrode, creating an extended electric field control region. This dimensional extension allows the electric field to be distributed over a larger area, reducing peak field concentration at the drain while maintaining the vertical current flow path necessary for high power output.
2Power
If conventional LDMOS transistor structure is used, then high current handling capability is achieved, but breakdown voltage is reduced due to electric field concentration
Solution Approach 1:
The field plate serves as a mediator structure that redistributes the electric field in the drain region. By introducing this intermediate electrode, the peak electric field that would normally cause premature breakdown is reduced, thereby increasing the breakdown voltage while preserving the high current handling capability of the LDMOS transistor.
Solution Approach 2:
The field plate modifies the electric field distribution parameter in the drain region by extending the field control laterally. This parameter change in electric field distribution reduces peak field concentration, thereby increasing breakdown voltage without compromising the current handling capability determined by the channel and drain structure.
3Reliability
If field plate is added to distribute electric field, then breakdown voltage is enhanced, but device complexity increases
Solution Approach 1:
The field plate is merged with the existing gate electrode structure, extending laterally from the gate into the drain region. This merging approach allows the field plate function to be integrated into the existing device architecture rather than adding a completely separate structure, thereby reducing the increase in device complexity while still achieving breakdown voltage enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces peak electric fields, suppresses hot carrier effects, and enhances breakdown voltages, leading to improved performance and reliability of power MOSFETs.
Implementation Method 1
a field plate adapted to distribute the electric field more evenly, reducing its peak value on the drain side
Implementation Method 2
first and second metal silicide layers respectively over the gate electrode and the field plate electrode
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate, first and second source/drain features, a gate dielectric layer, a gate electrode, a field plate electrode, first and second metal silicide layers, a dielectric layer, and a spacer. The gate electrode and the field plate electrode are over the gate dielectric layer and respectively vertically overlapping a well region and a drift region in the semiconductor substrate. A first sidewall of the field plate electrode faces the gate electrode. The first and second metal silicide layers are over the gate electrode and the field plate electrode, respectively. The dielectric layer has a first portion between the gate electrode and the first sidewall of the field plate electrode and a second portion below a bottom surface of the field plate electrode. The spacer is alongside a second sidewall of the field plate electrode and over the second portion of the dielectric layer.