LDMOS Field Plate Structure for Higher Breakdown Voltage
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Solution Overview
Problem
Power MOSFETs, particularly LDMOS transistors, face challenges in managing high voltages and frequencies effectively, leading to peak electric field distribution issues that can result in hot carrier effects and reduced breakdown voltages.
Innovation Solution
The integration of a field plate in the LDMOS device, combined with a BCD process technology, balances the electric field distribution and reduces peak values, achieved through specific doping and dielectric layer formations, allowing for the formation of a smart power integrated circuit that includes bipolar, CMOS, and LDMOS transistors on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional LDMOS transistor design is used, then high power output and high efficiency are achieved, but peak electric field distribution issues occur leading to hot carrier effects and reduced breakdown voltages
Solution Approach 1:
The transistor structure is segmented into distinct regions with different doping concentrations and types (e.g., lightly-doped drift region, heavily-doped buffer region, n-type and p-type zones). This segmentation allows each region to be optimized for its specific function, distributing the electric field more evenly and preventing peak field concentrations that cause breakdown.
Solution Approach 2:
Different regions of the transistor are given different local properties through selective doping (n-type, p-type, lightly-doped, heavily-doped zones). Each region's doping profile is locally optimized to control electric field distribution, with lightly-doped regions spreading the field and heavily-doped regions providing stability, thereby improving breakdown voltage without sacrificing power output.
2Reliability
If higher breakdown voltages are achieved through doping modifications, then hot carrier effects are suppressed, but device complexity increases
Solution Approach 1:
Multiple doping functions are merged into a single integrated doping profile structure. The patent combines lightly-doped drift regions, heavily-doped buffer regions, and junction formations into one continuous doping architecture that achieves both high breakdown voltage and hot carrier suppression without requiring separate discrete structures for each function.
Solution Approach 2:
The doping structure is designed to perform multiple functions simultaneously: the lightly-doped drift region both extends the depletion layer for higher breakdown voltage and distributes the electric field to suppress hot carrier effects. The heavily-doped buffer region simultaneously provides electrical stability and defines the junction characteristics, reducing the need for additional separate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the performance of high voltage transistors by reducing peak electric fields, suppressing hot carrier effects, and achieving higher breakdown voltages, while also allowing for lower on-resistance and gate charge, thereby improving the overall efficiency and reliability of the power MOSFETs.
Implementation Method 1
balances the electric field distribution and reduces peak values
Implementation Method 2
achieved through specific doping and dielectric layer formations
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.