LDMOS Gate-Field Plate Oxide Layout for Lower Ron
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LDMOS transistor devices face challenges in enhancing electrical performance, voltage endurance, and on-resistance (Ron) as the requirements for high-voltage power devices continue to increase.
Innovation Solution
The semiconductor device incorporates a first oxide layer and a second oxide layer disposed under and above the gate structure, respectively, along with a field plate, to reduce on-resistance and modify the electric field distribution, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then device simplicity and manufacturing ease are maintained, but on-resistance is high and electrical performance is limited
Solution Approach 1:
The patent implements nested oxide layers where a first oxide layer is positioned between the gate structure and drift region, and a second oxide layer is positioned between the first oxide layer and the gate structure. This nested configuration allows multiple functional layers to be integrated within the gate structure region, reducing on-resistance through enhanced electric field control without significantly increasing overall device footprint or manufacturing complexity
Solution Approach 2:
The patent introduces vertical layering of oxide layers beneath and above the gate structure, transitioning from a conventional planar structure to a multi-dimensional configuration. The first oxide layer extends vertically between the gate and drift region, while the second oxide layer adds another vertical dimension above the first oxide layer, enabling improved electric field distribution and reduced on-resistance through three-dimensional space utilization
2Reliability
If oxide layers are added under and above the gate structure, then on-resistance is reduced and breakdown voltage is enhanced, but device structure becomes more complex
Solution Approach 1:
The patent applies oxide layers with specific properties at specific locations: the first oxide layer is positioned where it can effectively modulate the electric field between the gate and drift region to reduce on-resistance, while the second oxide layer is positioned above the first oxide layer to enhance breakdown voltage. Each oxide layer is strategically placed to provide localized electric field control, optimizing performance without requiring uniform modification throughout the entire device structure
Solution Approach 2:
The patent employs a composite structure combining multiple oxide layers with different positions and functions. The first oxide layer and second oxide layer form a composite dielectric system beneath and above the gate structure, creating a multi-layered electric field management system that simultaneously achieves reduced on-resistance and enhanced breakdown voltage through the synergistic effect of the combined oxide layer configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively reduces on-resistance and enhances breakdown voltage, while maintaining process compatibility by adjusting the thickness and placement of oxide layers to optimize electric field distribution.
Implementation Method 1
a first oxide layer and a second oxide layer are disposed under a gate structure and disposed above the gate structure respectively for reducing on-resistance (Ron) of the semiconductor device and/or modifying electric field distribution
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.