LDMOS Field Plate Structure for Snap-Back Ruggedness
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Solution Overview
Problem
Existing microelectronic devices, such as DC-DC converters, face challenges in improving performance, reducing die size, and increasing the safe operating area (SOA) as they are scaled to newer generations, particularly in preventing snap-back breakdown and enhancing ruggedness.
Innovation Solution
The implementation of drain extended metal oxide semiconductor (MOS) transistors, specifically DEMOS transistors, with an unsilicided space adjacent to the drain ohmic contact regions, along with a field plate that overlaps the drain region, to terminate electric field lines and reduce breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional LDMOS devices are scaled to next generation, then device performance and power density improve, but snap-back breakdown occurs and ruggedness deteriorates
Solution Approach 1:
The field plate is positioned to preemptively terminate electric field lines before they can reach the drain region and cause snap-back breakdown. This preliminary field termination prevents the harmful electrical stress from developing in the first place, allowing the device to operate at higher power densities without sacrificing ruggedness
Solution Approach 2:
The field plate acts as an intermediary structure between the gate and drain regions, mediating the electric field distribution. By introducing this intermediate element, the patent controls the field lines to prevent direct interaction between high-voltage drain fields and the channel, thereby preventing breakdown while maintaining power efficiency
2Reliability
If drain region is extended to improve SOA, then safe operating area increases, but breakdown voltage control becomes difficult
Solution Approach 1:
The field plate modifies the electric field distribution parameters in the drain region, changing the field line trajectories and density. This parameter change allows the device to achieve a larger safe operating area while maintaining controlled breakdown characteristics, as the field plate effectively redistributes the electrical stress
3Reliability
If field plate is added to terminate electric field lines, then breakdown voltage is reduced and snap-back is prevented, but device complexity increases
Solution Approach 1:
The field plate serves multiple functions simultaneously: it terminates electric field lines to prevent snap-back breakdown, controls breakdown voltage, and enhances the safe operating area. By consolidating these multiple protective and performance-enhancing functions into a single structure, the patent avoids the need for multiple separate components, thereby limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ruggedness and safe operating area of microelectronic devices by reducing the drain-to-source breakdown voltage and preventing snap-back breakdown, while also improving impact ionization performance.
Implementation Method 1
a field plate that overlaps the drain region, to terminate electric field lines and reduce breakdown voltage
Data Source
AI summary
A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.


