LDMOS Field Plate Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional field plate structures in LDMOS devices enhance breakdown voltage but introduce parasitic feedback capacitance, negatively impacting high-frequency performance due to additional phase variations and signal modulation, making them unsuitable for high-speed switching applications.
Innovation Solution
A novel field plate structure is introduced in LDMOS devices, featuring a shielding structure with reduced overlap area between the gate and drain, which is electrically isolated by an insulating layer, to minimize parasitic gate-to-drain capacitance without degrading breakdown voltage or on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional field plate structure is used in LDMOS devices, then breakdown voltage is enhanced, but parasitic gate-to-drain capacitance increases, degrading high-frequency performance
Solution Approach 1:
The field plate structure is segmented into multiple sections with different conductivity types. Specifically, a first field plate region with first conductivity type and a second field plate region with second conductivity type are formed adjacent to each other over the drift region. This segmentation allows each region to contribute differently to electric field modulation, enhancing breakdown voltage while reducing parasitic capacitance through optimized charge distribution.
Solution Approach 2:
Different regions of the field plate are assigned different conductivity types to create locally optimized electric field characteristics. The first conductivity type region provides one type of field modulation while the second conductivity type region provides complementary modulation, allowing precise control of electric field distribution under the field plate structure. This local quality differentiation enables simultaneous improvement of breakdown voltage and reduction of parasitic capacitance.
2Area of stationary object
If the gate and shielding structure are positioned close together, then device area is reduced, but parasitic capacitance increases due to larger overlap area
Solution Approach 1:
The field plate is divided into segmented regions with alternating conductivity types that are positioned in specific patterns. This segmentation creates regions of reduced overlap between gate and field plate while maintaining overall compact device area. The alternating conductivity regions provide electric field modulation without requiring large lateral separation distances.
Solution Approach 2:
The conductivity type parameter is changed across different field plate regions to optimize the electric field distribution. By alternating between first and second conductivity types in adjacent regions, the structure achieves effective electric field control with minimal gate-to-field-plate overlap area, thereby reducing parasitic capacitance while maintaining compact dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic capacitance and switching loss, enabling higher frequency applications while maintaining power and linearity performance, thus enhancing the device's high-frequency performance without the need for costly materials or processes.
Implementation Method 1
A gate is formed over at least a portion of the body region and between the source and drain regions, the gate being electrically isolated from the body region by a first insulating layer disposed between the gate and the body region
Implementation Method 2
A field plate structure in an LDMOS device has been shown to not only enhance breakdown voltage in the LDMOS device but also to suppress a surface state
Implementation Method 3
The large gate polysilicon area also helps to accumulate electrons in the drift region under the field plate during an on-state of the LDMOS device, thereby reducing an on-resistance (RDSon) of the device
Data Source
AI summary
An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.