LDMOS Field Plate Work Function Engineering
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Solution Overview
Problem
LDMOS transistors face challenges in achieving high breakdown voltage while maintaining low parasitic resistance due to the inverse relationship between breakdown voltage and parasitic resistance, primarily attributed to the n− drift region's lower doping concentration.
Innovation Solution
A field plate with a higher work function than the gate stack is formed coplanar with the gate electrode, and a high-k metal gate is used for channel control, widening the depletion width and reducing the peak electric field, thereby increasing the breakdown voltage while keeping parasitic resistance low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the n− drift region doping concentration is reduced to increase breakdown voltage, then breakdown voltage increases, but parasitic resistance increases
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in specific regions: the n− drift region has low doping for high breakdown voltage, while the n− extension region has higher doping to reduce parasitic resistance. This spatial variation in doping quality allows simultaneous optimization of both breakdown voltage and resistance characteristics.
Solution Approach 2:
The drift region is segmented into two distinct parts: the main n− drift region and the n− extension region. This segmentation allows each region to be independently optimized - the drift region for breakdown voltage and the extension region for resistance reduction - thereby resolving the contradiction between these two parameters.
2Reliability
If a field plate is added to widen depletion width and increase breakdown voltage, then breakdown voltage increases, but device complexity increases
Solution Approach 1:
The patent merges the field plate function with the gate structure by forming the field plate as an extension of the gate electrode. This integration achieves the depletion width extension and breakdown voltage improvement while avoiding the complexity of separate field plate structures, as the field plate is formed concurrently with the gate during the same fabrication process.
Solution Approach 2:
The gate structure serves multiple functions: it controls the channel (traditional gate function) and simultaneously acts as a field plate to extend the depletion region and increase breakdown voltage. This multi-functionality eliminates the need for additional dedicated field plate structures, reducing device complexity while achieving high breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the breakdown voltage of LDMOS transistors while maintaining low parasitic resistance, enhancing their operational range and efficiency in applications such as automobiles, display electronics, and power converters.
Implementation Method 1
forming a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack
Implementation Method 2
The field plate helps widen the depletion width/reduce the peak electric field at the surface of the n− drift region, which in turn allows the device to sustain a larger voltage before breakdown occurs
Implementation Method 3
a high-k metal gate is used for channel control, widening the depletion width and reducing the peak electric field
Data Source
AI summary
An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.