LDMOS Fin Structure Gate Design for Dielectric Breakdown
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Solution Overview
Problem
The gate dielectric layer in existing LDMOS devices is prone to breakdown due to high electric fields, particularly in the drift region where the distance between the gate dielectric and the drain region is small, leading to potential leakage currents and reduced device reliability.
Innovation Solution
The fabrication method involves forming fin structures on a substrate with an isolation layer that covers the sidewall of an opening in the isolation region, ensuring the gate structure covers only the top surfaces and not the sidewall, thereby maintaining a larger distance from the drain region and reducing the electric field on the gate dielectric layer, which is made of high-k materials to enhance durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate dielectric layer is placed close to the drain region to reduce device area, then the device area is reduced, but the electric field strength increases causing gate dielectric breakdown
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional folded gate structure. The gate electrode is bent into multiple segments (first gate electrode segment, second gate electrode segment, third gate electrode segment) that fold back over the drift region. This dimensional change allows the gate to maintain electrical proximity to the channel while physically distancing the gate dielectric from the high-field drain region, thereby reducing breakdown risk without increasing footprint area.
Solution Approach 2:
The folded gate structure implements a nested configuration where the second gate electrode segment is positioned between the first and third segments, creating a nested arrangement. The gate dielectric layers are similarly nested between the gate electrode segments and the drift region. This nesting allows multiple functional layers to occupy overlapping spatial volumes, maximizing space utilization while maintaining the required electrical field distribution and preventing gate dielectric breakdown.
2Reliability
If high-k materials are used for gate dielectric to enhance durability, then the dielectric strength is improved, but the fabrication complexity increases
Solution Approach 1:
The patent changes the dielectric constant parameter by transitioning from traditional silicon dioxide (k≈3.9) to high-k materials such as hafnium oxide (k≈25) or aluminum oxide (k≈10). This parameter change allows for thinner effective dielectric thickness while maintaining or improving breakdown voltage, thereby enhancing dielectric strength without proportionally increasing physical thickness. The fabrication process incorporates standard atomic layer deposition (ALD) techniques for high-k material deposition, which, while adding process steps, utilizes established semiconductor manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the LDMOS device's ability to sustain high voltages by reducing leakage currents and preventing gate dielectric breakdown, improving the overall performance and reliability of the device.
Implementation Method 1
An opening is formed in the fin structures in the isolation region. The isolation layer is formed in the opening and covers a sidewall of the opening formed by a portion of each fin structure in the first device region. The isolation layer exposes the top surfaces of the plurality of fin structures.
Implementation Method 2
The gate structure is formed across each fin structure in the first device region. The gate structure covers a portion of the sidewall and the top surfaces of the fin structure formed in the first device region and also covers the top surface of the isolation layer.
Implementation Method 3
The impurity concentration in the drift region is relatively low. When an LDMOS device receives a high voltage, the device may be able to sustain such a high voltage because of the high resistance of the drift region.
Implementation Method 4
one implantation process may introduce arsenic (As) ions with a relatively high concentration into the substrate, while the other implantation process may introduce boron (B) ions with a relatively low concentration
Implementation Method 5
After performing the two ion implantation processes, a high temperature annealing process is performed. During the high temperature annealing process, boron ions often diffuse quicker than arsenic ions
Data Source
AI summary
The present disclosure provides a laterally diffused metal-oxide-semiconductor (LDMOS) device. The LDMOS device includes a plurality of fin structures formed on a substrate including a first device region, a second device region, and an isolation region sandwiched between the two regions. An opening is formed in the fin structures in the isolation region. The LDMOS device further includes an isolation layer formed in the opening and covering the sidewall of the opening formed by a portion of each fin structure in the first device region. The isolation layer exposes top surfaces of the plurality of fin structures. Moreover, the LDMOS device also includes a gate structure formed across each fin structure in the first device region. The gate structure covers a portion of the sidewall and the top surfaces of the fin structure formed in the first device region and also covers the top surface of the isolation layer.