LDMOS FinFET Structures with Multiple Gate Control
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Solution Overview
Problem
Current field-effect transistor structures for laterally-diffused metal-oxide-semiconductor (LDMOS) devices lack improved performance and higher breakdown voltage capabilities necessary for high-voltage integrated circuits, such as those used in microwave/RF power amplifiers.
Innovation Solution
The structure and method involve forming first and second fins on a substrate with strategically positioned wells and gate structures, including a doped region between the gate structures, which enhances control over the channel and increases breakdown voltage through the use of a moat region and a doped region with opposite conductivity types, allowing for improved carrier control and voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar field-effect transistor structures are used, then manufacturing is simpler, but leakage current is higher and control over the channel is reduced
Solution Approach 1:
The patent employs a FinFET structure where the gate electrode wraps around the channel in a three-dimensional configuration, creating a curved surface geometry that provides superior channel control compared to planar structures. This curved gate configuration reduces leakage current by improving the electric field distribution across the channel.
Solution Approach 2:
The patent transitions from a two-dimensional planar transistor structure to a three-dimensional FinFET architecture by forming vertical fins that extend upward from the substrate. This addition of the vertical dimension increases the effective channel width and improves gate control without increasing the planar footprint, thereby reducing leakage current.
2Reliability
If conventional LDMOS structures are used, then high voltage handling is achieved, but performance and breakdown voltage capabilities are insufficient for advanced high-voltage integrated circuits
Solution Approach 1:
The patent divides the channel region into multiple segments by creating separate first and second fins with distinct source/drain regions and doping configurations. This segmentation allows independent optimization of different channel portions to enhance breakdown voltage capability while managing the complexity through modular design.
Solution Approach 2:
The patent implements different doping concentrations and types in specific regions - heavily-doped source/drain regions in one fin versus lightly-doped regions in another fin, and different doping in the first and second wells. This local quality variation optimizes carrier control and breakdown characteristics in different parts of the device to improve overall reliability.
3Object-generated harmful factors
If higher threshold voltages are used to reduce leakage current, then leakage is reduced, but carrier flow control becomes less efficient
Solution Approach 1:
The patent creates a dynamic threshold voltage characteristic by implementing multiple gate structures that can be independently controlled. The first and second gate electrodes can apply different voltages to different fin regions, allowing dynamic adjustment of the threshold voltage to optimize both leakage reduction and carrier flow efficiency under different operating conditions.
Solution Approach 2:
The patent utilizes different doping concentrations and types in various regions to create distinct electrical characteristics. The heavily-doped source/drain regions provide strong carrier injection, while the lightly-doped channel regions maintain low leakage, achieving both goals simultaneously through parameter optimization rather than relying solely on high threshold voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces leakage current, enables lower threshold voltages, and increases the breakdown voltage of the field-effect transistor, leading to improved performance and reduced power consumption in high-voltage applications.
Implementation Method 1
A doped region is arranged within the second well in the first fin between the first gate structure and the second gate structure, and has the first conductivity type
Implementation Method 2
When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current
Implementation Method 3
The first well has a first conductivity type, and the second well has a second conductivity type
Data Source
AI summary
Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.