LDMOS Transistor Floating Ring Stabilization
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Solution Overview
Problem
Conventional laterally diffused metal-oxide-semiconductor field-effect transistors with a RESURF structure suffer from higher gate-drain capacitance (Cgd) and poor dynamic characteristics due to the floating P-type ring, which fails to timely release minority carrier charges, leading to charge accumulation and increased switching losses.
Innovation Solution
Incorporating trench polysilicon electrodes that extend through a floating P-type ring, providing capacitive coupling to stabilize the ring's potential and reduce gate-drain capacitance, while also enhancing the electric field and withstand voltage through silicon oxide properties, and adjusting doping concentrations to minimize on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a floating P-type ring is used in the drift region, then the breakdown voltage is improved, but the gate-drain capacitance increases and dynamic characteristics deteriorate
Solution Approach 1:
The patent introduces an N-type region as an intermediary between the floating P-type ring and the drain, creating a P-N junction that actively manages charge accumulation. This intermediary structure prevents direct charge buildup on the floating ring while maintaining the high breakdown voltage benefit, thereby resolving the contradiction between voltage strength and dynamic performance
Solution Approach 2:
The patent modifies the electrical parameters by creating a controlled P-N junction with specific doping concentrations. By adjusting the doping levels in the N-type region and configuring the P-N junction characteristics, the device achieves both high breakdown voltage and reduced charge accumulation, improving dynamic characteristics without sacrificing voltage strength
2Strength
If the floating P-type ring is used, then the RESURF effect is achieved, but charge accumulation occurs leading to higher Cgd
Solution Approach 1:
The N-type region serves as a mediator that intercepts and redirects charge flow before it can accumulate on the floating P-type ring. This intermediary layer maintains the RESURF effect for high withstand voltage while preventing charge buildup that would increase Cgd, thus resolving the contradiction between voltage strength and capacitance
Solution Approach 2:
The patent extracts the charge accumulation problem by introducing the N-type region that actively removes excess charges from the drift region before they can reach the floating P-type ring. This extraction mechanism maintains the beneficial RESURF effect while eliminating the harmful charge accumulation that increases gate-drain capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate-drain capacitance, improves dynamic characteristics, and increases the device's withstand voltage by stabilizing the floating ring's potential and reducing on-resistance, thereby enhancing the transistor's performance.
Implementation Method 1
the potential of the floating ring is relatively stable due to the capacitive coupling of the trench polysilicon electrode
Implementation Method 2
Due to the material property of the silicon oxide outer wall, its critical electric field becomes higher (three times higher than the electric field in silicon), the influence of an additional electric field introduced by the floating P-type ring 50 on the total electric field of the device is weakened, and the withstand voltage of the device is improved
Data Source
AI summary
A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.