LDMOS on Fully Depleted SOI for Low On-Resistance
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Solution Overview
Problem
Laterally diffused MOSFETs (LDMOS) on fully depleted SOI face challenges with high on-state resistance due to the lightly doped drain (LDD) segment, which hinders fast turn-on performance, despite providing higher breakdown voltages and preventing gate dielectric breakdown.
Innovation Solution
Applying the gate voltage concurrently to the channel and a semiconductor well behind the buried oxide layer to enhance drain-to-source current, thereby reducing on-state resistance without additional process steps or masks, and maintaining performance in the off-state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lightly doped drain (LDD) segment is used in LDMOS on FDSOI, then breakdown voltage is improved and gate dielectric breakdown is prevented, but on-state resistance increases which hinders fast turn-on performance
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration profile in the drain region. Specifically, it uses a graded doping profile where the doping concentration increases from the gate edge toward the bulk, creating regions with different doping levels (lightly doped near gate, heavily doped in bulk). This gradient approach allows the structure to achieve both high breakdown voltage (through the lightly doped region) and low on-state resistance (through the heavily doped region), resolving the technical contradiction between these two parameters.
2Manufacturing precision
If the LDD segment is removed to reduce on-state resistance, then fast turn-on performance is improved, but breakdown voltage decreases and gate dielectric breakdown risk increases
Solution Approach 1:
The patent applies local quality by creating spatially varying doping concentrations within the drain region. The doping profile is designed to have different local properties: a lightly doped region adjacent to the gate for voltage drop and field control, and a heavily doped region toward the bulk for low resistance. This local differentiation allows each region to fulfill its specific function, achieving both low on-state resistance and high breakdown voltage simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces on-state resistance by up to 30% while maintaining the benefits of higher breakdown voltages and preventing gate dielectric breakdown, enhancing the overall performance of LDMOS on FDSOI.
Implementation Method 1
the gate voltage is applied to the channel to create an inversion layer in the channel
Implementation Method 2
the gate voltage may be applied to a semiconductor well behind the buried oxide layer to create a back bias and thus enhance the drain to source current
Data Source
AI summary
Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.