LDMOS Gate Replacement Layout to Prevent CMP Hump Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating laterally diffused metal-oxide-semiconductor (LDMOS) transistors as the process node shrinks, particularly due to issues with the chemical-mechanical polishing (CMP) process being hindered by humps formed during the metal gate replacement process, which affects the formation of the gate metal structure.
Innovation Solution
The method involves patterning a dielectric layer to avoid overlaying the top surface of the sacrificial gate structure, preventing the formation of humps and ensuring successful exposure of the sacrificial gate structure for replacement with a new gate structure, thereby facilitating a smooth CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the dielectric layer is patterned to avoid overlaying the top surface of the sacrificial gate structure, then the CMP process is not hindered and the sacrificial gate structure can be successfully exposed for replacement, but the manufacturing complexity increases due to additional patterning steps
Solution Approach 1:
The dielectric layer is patterned in advance before the CMP process to prevent hump formation. This preliminary patterning action ensures that subsequent CMP and gate replacement steps can proceed without interference, resolving the contradiction by preparing the structure beforehand to avoid later process hindrances.
2Productivity
If the process node is shrunk to improve integration density, then more electronic components can be integrated, but new techniques are needed to maintain transistor performance such as low gate-to-drain capacitance and high breakdown voltage
Solution Approach 1:
The patent employs specific parameter changes in the dielectric layer patterning process, including controlling the patterning conditions and dielectric material properties, to achieve the precise geometric configurations needed for maintaining transistor performance at scaled dimensions while enabling continued integration density improvement.
Data Source
AI summary
A semiconductor device includes an active gate metal structure disposed over a substrate, the active gate metal structure having a first sidewall and a second sidewall opposite to each other. The semiconductor device includes a first source/drain region disposed adjacent the first sidewall of the active gate metal structure with a first lateral distance. The semiconductor device includes a second source/drain region disposed adjacent the second sidewall of the active gate metal structure with a second lateral distance, wherein the second lateral distance is substantially greater than the first lateral distance. The semiconductor device includes a resist protective oxide (RPO) comprising a first portion extending over a portion of a major surface of the substrate that is laterally located between the second sidewall and the second source/drain region, wherein the RPO has no portion extending over a top surface of the active gate metal structure.