LDMOS Transistor Gate-Connected Conductive Structure for Breakdown Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
LDMOS transistors face challenges in maintaining high breakdown voltage as device dimensions reduce, leading to junction avalanche breakdown phenomena near the drain region due to low junction breakdown voltage.
Innovation Solution
A conductive structure is disposed on an isolation structure adjacent to the drain region, enhancing the junction avalanche breakdown voltage by forming a polysilicon conductive structure that surrounds the drain region and is connected to the gate, thereby maintaining the breakdown voltage even with reduced device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimension is reduced, then device integration and density are improved, but junction breakdown voltage decreases leading to avalanche breakdown
Solution Approach 1:
A conductive structure is introduced as an intermediary element between the gate and the drain region. This conductive structure includes a first conductive region extending from the gate into the drift region, and a second conductive region surrounding the drain region. The intermediary conductive structure modifies the electric field distribution, preventing direct avalanche breakdown between the gate and drain while maintaining reduced device dimensions.
Solution Approach 2:
The conductive structure extends in multiple spatial dimensions: the first conductive region extends vertically from the gate into the drift region, while the second conductive region forms a horizontal ring surrounding the drain region. This multi-dimensional configuration allows the conductive structure to effectively control the electric field in three-dimensional space, maintaining breakdown voltage without increasing the device's planar footprint.
2Reliability
If conductive structure is added to enhance breakdown voltage, then reliability is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The conductive structure is merged with the existing gate electrode, forming an integrated gate-conductive structure. The first conductive region is electrically connected to the gate, and the second conductive region is connected to the first conductive region, creating a unified structure that performs both gating and breakdown protection functions. This merging approach avoids adding separate complex components while achieving the desired reliability improvement.
Solution Approach 2:
The conductive structure serves multiple functions simultaneously: it acts as part of the gate electrode for device switching, modifies the electric field distribution to prevent avalanche breakdown, and provides electrostatic discharge protection. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity while achieving improved reliability.
3Reliability
If conductive structure is added to enhance breakdown voltage, then reliability is improved, but manufacturing process steps and cost increase
Solution Approach 1:
The conductive structure is formed during the preliminary gate electrode fabrication process. The conductive material is deposited and patterned to create both the gate region and the conductive structure in a single fabrication sequence. This preliminary action integrates the breakdown protection feature into the existing manufacturing flow without requiring additional dedicated process steps, thereby maintaining ease of manufacture while improving reliability.
Solution Approach 2:
The formation of the conductive structure is merged with the gate electrode fabrication process. The same conductive material deposition and patterning steps that create the gate electrode also create the conductive structure with the first and second conductive regions. This merging of fabrication steps eliminates the need for separate manufacturing processes, thereby avoiding additional manufacturing complexity and cost while achieving the desired reliability improvement.
Data Source
AI summary
A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.