LDMOS Gate Drivers with 3D Interconnects
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Solution Overview
Problem
Lateral power switches, particularly LDMOS devices, face challenges with increased resistance and output capacitance due to tight metal widths and overlapping drain and source metal, leading to voltage and power losses, and 'shoot through' conditions in power management applications, where high-speed interconnection configurations are needed.
Innovation Solution
A semiconductor device with a semiconductor die featuring LDMOS cells, metallic layers, and gate drivers positioned along the periphery, using distributed three-dimensional decoupling with metallic pillars to reduce impedance and improve timing synchronization of gate signals, thereby reducing resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If deep sub-micron lithography is used to reduce cell pitch below five microns, then device size is reduced and integration density is improved, but metal widths decrease leading to increased resistance between drain/source terminals and external package pins
Solution Approach 1:
The patent transitions from planar two-dimensional routing to three-dimensional routing by stacking multiple metal layers vertically. This allows interconnect paths to extend in the vertical dimension, providing additional routing resources and enabling lower resistance paths that bypass the limitations of reduced horizontal metal widths in deep sub-micron processes.
Solution Approach 2:
The patent combines multiple metal layers into an integrated three-dimensional interconnect structure, merging the routing functions of individual layers into a unified system. This consolidation creates redundant and parallel current paths, reducing overall resistance and providing multiple routes for current flow between drain/source terminals and external package pins.
2Volume of moving object
If deep sub-micron lithography is used to reduce cell pitch, then device size is reduced, but drain and source metal overlap increases leading to increased output capacitance (Coss)
Solution Approach 1:
The patent separates drain and source metal connections into different vertical layers, utilizing the third dimension to prevent horizontal overlap. By routing drain and source metals on separate metal layers with appropriate isolation, the design reduces parasitic capacitance while maintaining the compact footprint enabled by deep sub-micron lithography.
Solution Approach 2:
The patent segments the interconnect structure into multiple isolated metal layers, with drain and source connections separated in the vertical dimension. This segmentation prevents unwanted capacitive coupling between drain and source metals, reducing output capacitance while maintaining signal integrity and enabling high-speed operation.
3Adaptability or versatility
If interior portions of LDMOS cells are routed to periphery package pins, then external connectivity is achieved, but voltage and power losses increase due to longer internal connection paths
Solution Approach 1:
The patent uses vertical stacking of metal layers to create shorter three-dimensional current paths from interior LDMOS cell portions to periphery package pins. By utilizing the vertical dimension for direct routing, the design reduces the horizontal travel distance and associated resistance, minimizing voltage and power losses while maintaining external connectivity.
Solution Approach 2:
The patent implements localized interconnect structures with varying metal layer configurations optimized for different regions of the device. Interior regions use multi-layer vertical routing to minimize path length, while periphery regions are optimized for package pin connections, creating locally optimized current paths that reduce overall voltage and power losses.
4Reliability
If source, drain, and gate lines are electrically distant from signal generator, then device functionality is maintained, but delay lines are created causing gradual turn-on/turn-off behavior and shoot through conditions
Solution Approach 1:
The patent positions gate drivers around the periphery of the semiconductor die and uses vertical three-dimensional interconnects to deliver gate signals directly to LDMOS cells. This vertical routing approach equalizes the electrical distance from the signal generator to all gate lines, eliminating delay lines and ensuring simultaneous turn-on/turn-off behavior across all cells, thereby preventing shoot through conditions while maintaining device functionality.
Solution Approach 2:
The patent pre-positiones gate drivers around the periphery of the die to minimize signal path lengths to all LDMOS cells. By strategically locating drivers close to their respective cell groups and using vertical interconnects, the design equalizes signal arrival times at all gates, ensuring synchronized switching action and preventing harmful shoot through currents.
Data Source
AI summary
A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.