LDMOS Gate Electrode Overlap Reduction for Breakdown Voltage
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Solution Overview
Problem
Conventional LDMOS transistors face limitations in breakdown voltage and on-resistance due to restrictions in the overlapping distance between the gate structure and the body region, which hampers the increase of breakdown voltage and reduction of on-resistance.
Innovation Solution
A method involving two etching processes and a first ion implantation process is used to form a body region under the gate electrode, allowing the gate electrode to cover and control the body region with a reduced overlapping area, thereby increasing the breakdown voltage and decreasing the on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode covers a larger area including the body region, then the breakdown voltage increases, but the manufacturing complexity increases due to requiring two etching processes
Solution Approach 1:
The gate electrode formation is divided into two distinct etching processes: a first etching process that defines the initial gate structure, and a second etching process that extends the gate electrode to cover the body region. This segmentation allows precise control over the gate electrode's final geometry, enabling it to cover a larger area for improved breakdown voltage while maintaining manufacturing feasibility through standardized process steps.
Solution Approach 2:
The body region is formed through ion implantation before the gate electrode is fully formed. This preliminary action allows the gate electrode to subsequently cover and control the body region, as the body region already exists in the substrate when the gate material is deposited and patterned. This sequence enables the gate to extend over the body region for enhanced voltage breakdown characteristics.
2Reliability
If the gate electrode covers a larger area including the body region, then the on-resistance decreases, but the manufacturing precision requirements increase
Solution Approach 1:
The etching process is segmented into two distinct stages with different precision requirements. The first etching process establishes the basic gate structure with standard precision, while the second etching process extends the gate to cover the body region. This segmentation allows each etching step to be optimized independently, reducing the overall manufacturing precision burden compared to a single complex etching step.
Solution Approach 2:
The body region is pre-formed through ion implantation before gate electrode deposition, establishing a clear spatial reference. This preliminary action enables the subsequent etching processes to precisely target the body region for gate coverage without requiring extremely high precision throughout the entire fabrication sequence, as the body region boundaries are already defined.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively increases the breakdown voltage and reduces the on-resistance of LDMOS transistors by allowing the gate electrode to cover a larger area, enhancing the transistor's voltage durability and current capacity.
Implementation Method 1
performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.