LDMOS Gate Contact Field Plate for Lower Ron and Off-Current
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Solution Overview
Problem
Traditional LDMOS transistor devices face issues with high on-resistance (Ron), high off-current (Ioff), and short hot carrier injection life-time, limiting their performance and reliability.
Innovation Solution
A laterally diffused metal oxide semiconductor (LDMOS) design featuring a gate contact layer that functions as a field plate, electrically connected to a dummy contact structure on shallow trench isolation, disperses the electric field and inhibits the Kirk effect, enhancing the device's performance without requiring additional process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional LDMOS structure is used, then manufacturing is simple and integration is easy, but on-resistance is high and off-current is high
Solution Approach 1:
The gate structure is segmented into multiple components: gate electrode, gate dielectric layer, and gate contact layer. The gate contact layer is further divided into first and second gate contact layers with different doping types. This segmentation allows each layer to perform specific functions, reducing on-resistance and off-current while maintaining manufacturing simplicity.
Solution Approach 2:
Different regions of the gate contact layer are doped with different types of dopants (first dopant type in first gate contact layer, second dopant type in second gate contact layer). This local quality variation optimizes the electrical properties in different areas, reducing both on-resistance and off-current locally where needed.
2Device complexity
If traditional LDMOS structure is used, then device structure is simple, but hot carrier injection life-time is short
Solution Approach 1:
The gate contact structure is segmented into multiple doped layers (first gate contact layer with first dopant type, second gate contact layer with second dopant type). This segmentation creates optimized electric field distribution that protects against hot carrier injection, extending device life-time without significantly increasing structural complexity.
Solution Approach 2:
The gate contact structure uses composite doping configuration with both n-type and p-type doped layers. This composite structure creates beneficial electric field effects that reduce hot carrier injection damage, extending device operational life-time while maintaining reasonable structural complexity.
3Reliability
If field plate is extended using additional process steps, then current dispersion is improved, but manufacturing complexity increases
Solution Approach 1:
The gate contact layer is merged with the field plate structure, allowing the same layer to serve dual functions. The first and second gate contact layers extend to form an extended field plate that improves current dispersion without requiring separate fabrication process steps, thus improving reliability without increasing manufacturing complexity.
Solution Approach 2:
The gate contact layer serves multiple functions: it provides electrical contact to the gate electrode, forms an extended field plate for current dispersion, and creates optimized electric field distribution through its doped structure. This multi-functionality improves current dispersion while avoiding additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces off-current by 40%, on-resistance by 6%, and increases hot carrier injection life-time by 20%, while also enhancing breakdown voltage, thereby improving the overall quality and performance of the LDMOS transistor.
Implementation Method 1
The gate contact layer has the functions of dispersing electric field and inhibiting Kirk effect
Implementation Method 2
The gate contact layer has the functions of dispersing electric field and inhibiting Kirk effect
Data Source
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AI summary
The invention provides a laterally diffused metal-oxide-semiconductor (LDMOS), which comprises a substrate, a plurality of fin structures on the substrate, a gate structure on the substrate and spanning the fin structures, and a gate contact layer on the gate structure, wherein the gate contact layer is electrically connected with a dummy contact structure.