LDMOS Gate Structure for Hot Carrier Injection Mitigation

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Solution Overview

Problem

Conventional LDMOS devices suffer from 'hot carrier injection' (HCI) degradation, which limits their performance and reliability due to increased on-resistance and reduced breakdown voltage, especially when attempting to minimize on-resistance by increasing the doping concentration of the lightly-doped drain (LDD) region.

Innovation Solution

The introduction of an extended gate region within the shallow isolation trench structure, which employs the enhanced field plate effect to reduce impact ionization and increase breakdown voltage by extending the gate electrode into the shallow trench isolation structure, thereby reducing the impact of HCI and improving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the doping concentration of the lightly-doped drain (LDD) region is increased to minimize on-resistance, then on-resistance is reduced, but hot carrier injection (HCI) degradation increases

Engineering Contradiction:

Improveon-resistanceVSAvoidhot carrier injection degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a laterally diffused drain region with a specific doping profile that is lighter than conventional LDD regions. This localized modification of the doping concentration in the drain region reduces hot carrier injection degradation while maintaining acceptable on-resistance characteristics. The lighter doping concentration in the lateral drain region specifically addresses the HCI problem without requiring a complete redesign of the entire device structure.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the doping concentration parameter of the LDD region, using a lighter doping concentration compared to conventional designs. This parameter change directly addresses the technical contradiction by reducing the doping concentration to minimize HCI degradation and maintain breakdown voltage, while the overall device design compensates for any increase in on-resistance through other structural modifications.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces HCI degradation, allowing LDMOS devices to operate at more desirable voltage and current levels while maintaining or improving breakdown voltage and reducing fabrication complexity by eliminating the need for additional processing steps.

Implementation Method 1

employs the enhanced field plate effect to reduce impact ionization and increase breakdown voltage by extending the gate electrode into the shallow trench isolation structure

Methodology Applied

Scientific EffectField plate effect: Electric Field

Data Source

PatentUS9842903B2Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same

Publication Date: 2017.12.12 GLOBALFOUNDRIES SINGAPORE PTE LTD

AI summary

Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.