LDMOS Gate Pattern Layout for Uniform Oblique Ion Implantation
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Solution Overview
Problem
The reliability of semiconductor devices is compromised due to differences in impurity profiles between the outermost LDMOS and other LDMOS, leading to lower threshold voltage and increased leak current.
Innovation Solution
A manufacturing method involving anisotropic etching and oblique ion implantation using a resist pattern as a mask to form the body region, ensuring consistent impurity profiles across all LDMOS, with the dummy gate pattern positioned to allow optimal ion injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the body region is formed using only one gate pattern as a mask in the outermost LDMOS, then the manufacturing process is simplified, but the impurity profile of the body region differs from other LDMOS, causing lower threshold voltage and increased leak current
Solution Approach 1:
The patent divides the gate pattern structure into two distinct components: a gate pattern for forming the channel region and a dummy gate pattern positioned adjacent to it. This segmentation allows the dummy gate pattern to serve as an additional mask during oblique ion implantation, ensuring that the outermost LDMOS receives the same impurity profile treatment as other LDMOS structures, thereby resolving the reliability issue while maintaining manufacturing simplicity
Solution Approach 2:
The dummy gate pattern acts as an intermediary element that mediates the ion implantation process. By positioning the dummy gate pattern adjacent to the gate pattern and using it as a mask during oblique ion implantation, the patent ensures that ions are properly blocked and directed, creating a consistent impurity profile in the body region of the outermost LDMOS without complicating the overall manufacturing process
2Ease of manufacture
If the dummy gate pattern is positioned too far from the gate pattern, then the ion implantation process becomes simpler, but the impurity profile consistency is compromised
Solution Approach 1:
The patent optimizes the positional parameter of the dummy gate pattern by setting its distance from the gate pattern within a specific range (0.5-2.0 times the gate pattern width). This parameter adjustment ensures that the dummy gate pattern is close enough to effectively mask and direct ions during oblique ion implantation, maintaining consistent impurity profiles, while still being far enough to allow practical manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability of the semiconductor device by maintaining consistent threshold voltages and reducing leak current, thereby improving overall device performance.
Implementation Method 1
a step of performing anisotropic etching treatment using the first resist pattern as a mask to selectively remove the first conductive film exposed from the first resist pattern
Implementation Method 2
a step of performing oblique ion implantation using the first resist pattern as a mask to form a first body region of a first conductivity type in the semiconductor substrate
Data Source
AI summary
A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.