LDMOS Gate Oxide Structure for Higher Breakdown in Less Area
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Solution Overview
Problem
Conventional LDMOS transistor devices face challenges in enhancing electrical performance and increasing the density of high voltage semiconductor units, particularly in alleviating high voltage between the drain and source while maintaining a planar structure for integration with other circuits.
Innovation Solution
A semiconductor device with a gate oxide layer featuring a bottom extending downwards and a depressed top surface, positioned corresponding to the bottom, is used to improve electrical performance and reduce the occupied area, allowing for a longer current path and increased distribution density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar gate oxide layer is used in LDMOS transistor, then the device structure is simple and easy to manufacture, but the electrical performance is limited due to high edge electrical fields and short current path
Solution Approach 1:
The gate oxide layer is transformed from a conventional planar (2D) structure to a three-dimensional structure with a bottom extending downwards into the drift region and a depressed top surface. This dimensional change creates a longer current path through the drift region, reduces edge electrical fields, and improves hot carrier injection endurance without fundamentally changing the manufacturing process complexity
Solution Approach 2:
The gate oxide layer structure is designed to extend downwards into the drift region, creating a nested configuration where the oxide layer penetrates into the semiconductor substrate. This nested structure increases the effective area of the gate oxide interface with the drift region, thereby improving electrical performance while maintaining a compact device footprint
2Reliability
If the drift region area is increased to improve high voltage capability, then the breakdown voltage increases, but the device area occupied increases, reducing distribution density
Solution Approach 1:
By extending the gate oxide layer bottom downwards into the drift region, the current path length is increased without increasing the planar device footprint. This allows the drift region to be more efficiently utilized, maintaining high breakdown voltage capability while reducing the area occupied by the device and enabling higher distribution density
3Reliability
If the current path length is increased to improve electrical performance, then hot carrier injection endurance improves, but the device area increases, reducing productivity
Solution Approach 1:
The gate oxide layer is configured to extend downwards into the drift region, creating a three-dimensional current path that is longer than conventional planar structures. This extended current path improves hot carrier injection endurance by reducing electric field concentration, while the vertical extension rather than horizontal expansion maintains compact device area for high productivity
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.