LDMOS Gate Oxide Structure for High Breakdown Density
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Solution Overview
Problem
Conventional LDMOS transistor devices face challenges in enhancing electrical performance and increasing the density of high voltage semiconductor units, particularly in reducing the area occupied by the semiconductor device while maintaining high breakdown voltage.
Innovation Solution
A semiconductor device with a gate oxide layer featuring a bottom extending downwards and a depressed top surface is used, which includes a first and second portion, with the second portion positioned between the gate structure and the source/drain region, allowing for a longer current path and reduced area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar gate oxide layer is used, then the device structure is simple and easy to manufacture, but the current path is short resulting in poor electrical performance
Solution Approach 1:
The gate oxide layer transitions from a conventional planar (2D) structure to a three-dimensional structure with a bottom extending downward into the drift region and a depressed top surface. This dimensional change elongates the current path from the source to drain, improving electrical performance by increasing the effective channel length without proportionally increasing the device footprint.
Solution Approach 2:
The gate oxide layer structure embeds the extended bottom portion within the drift region, creating a nested configuration where the oxide layer penetrates downward into the semiconductor substrate. This nesting allows the current path to extend vertically into the drift region while maintaining a compact overall device structure.
2Reliability
If the device area is increased to improve electrical performance, then the current path can be elongated, but the distribution density of high voltage semiconductor units decreases
Solution Approach 1:
By extending the gate oxide layer vertically downward into the drift region rather than horizontally, the current path is elongated in the vertical dimension. This allows electrical performance improvement without increasing the horizontal device footprint, thereby maintaining high distribution density of semiconductor units.
Solution Approach 2:
The gate oxide layer exhibits non-uniform thickness and configuration, with an extended bottom portion positioned specifically in the drift region where it contributes to current path elongation. This localized structural modification optimizes electrical performance in the critical drift region without affecting other device areas.
3Reliability
If the gate oxide layer is extended downward into the drift region, then the current path is elongated improving electrical performance, but the manufacturing process becomes more complex
Solution Approach 1:
The gate oxide layer structure is designed and formed with the extended bottom portion and depressed top surface during the initial oxide formation process. By establishing this complex three-dimensional structure early in the manufacturing sequence, subsequent processing steps can proceed with standard planar techniques, avoiding the need for additional complex fabrication operations.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.