LDMOS Gate Shield and Deep Trench Contact for Higher SOA
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Solution Overview
Problem
Current LDMOS devices face challenges in increasing their safe operating area (SOA) and switching frequency, particularly in power amplifier applications, where existing technologies struggle to improve device ruggedness and reduce die size effectively.
Innovation Solution
The implementation of a deep trench contact and an optional source-coupled gate shield in LDMOS devices, along with a method of fabrication that includes forming a semiconductor substrate with epitaxial layers, gate dielectric layers, and field relief dielectric layers, enhances the device's conductivity and reduces parasitic effects, thereby improving SOA and switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS device structures are used, then manufacturing simplicity is maintained, but safe operating area (SOA) and switching frequency performance are limited
Solution Approach 1:
The device structure is segmented into distinct functional regions including deep trench contact regions, source-coupled gate shield regions, and conventional LDMOS regions. This segmentation allows each region to be optimized independently for its specific function while contributing to overall improved SOA and switching frequency performance.
Solution Approach 2:
A source-coupled gate shield is introduced as an intermediary structure between the gate electrode and the channel region. This gate shield acts as a mediator that reduces parasitic capacitance and electromagnetic field coupling, thereby improving switching frequency and SOA without fundamentally redesigning the entire device structure.
2Reliability
If device ruggedness is improved through increased SOA, then reliability is enhanced, but die size increases
Solution Approach 1:
Enhanced reliability features are localized to specific regions of the device rather than being implemented uniformly across the entire die. The deep trench contact and source-coupled gate shield are positioned in critical areas where they provide maximum benefit for improving SOA and ruggedness, while minimizing impact on overall die size.
3Productivity
If switching frequency is increased for power amplifier applications, then performance is improved, but parasitic effects and electromagnetic field coupling increase
Solution Approach 1:
The source-coupled gate shield serves as an intermediary structure that specifically targets and reduces parasitic capacitance and electromagnetic field coupling between the gate and drain regions. By positioning the gate shield in this critical location, parasitic effects are minimized, enabling higher switching frequency operation with reduced harmful interactions.
Solution Approach 2:
The harmful parasitic capacitance and electromagnetic field coupling are effectively 'taken out' or removed from the device operation by introducing the gate shield structure. The gate shield extracts or isolates the parasitic effects, preventing them from degrading switching frequency performance.
Data Source
AI summary
An LDMOS device includes a semiconductor substrate with an epitaxial layer that comprises a body region and a drain drift region. A drain region is formed in the drain drift region and a source region is formed in the body region. A gate shield may be formed over a gate shield dielectric layer disposed over a gate electrode, the gate shield having a variable length and tied to the source that is provided with a body connection via a deep trench contact.