LDMOS Gate Structure With Sidewall Contacts for Lower Gate Resistance
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Solution Overview
Problem
Conventional LDMOS devices face challenges in achieving low gate resistance and optimal gate-to-drain capacitance, which affect RF performance in power amplifiers.
Innovation Solution
The structure includes sidewall spacers over a semiconductor substrate with a gate structure comprising multiple layers such as high-k dielectric material, workfunction metal, and barrier material, where the gate electrode significantly increases in volume due to an etch back process, and the drain region is positioned farther from the gate structure than the source region, utilizing shallow trench isolation to improve capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode volume is increased to reduce gate resistance, then gate resistance decreases, but device area increases
Solution Approach 1:
The gate electrode is extended vertically along the sidewall spacers to increase its volume and reduce resistance without significantly increasing the planar device area. This three-dimensional configuration allows the gate electrode to wrap around the channel region, providing both low resistance and compact footprint.
Solution Approach 2:
The gate electrode is positioned within the space defined by the sidewall spacers, nesting the conductive structure within the existing device geometry. This allows the gate electrode to utilize the vertical space between the spacers to increase volume without expanding the lateral dimensions of the device.
2Reliability
If the drain region is positioned farther from the gate structure, then gate-to-drain capacitance improves, but device length increases
Solution Approach 1:
The drain region is positioned farther away in the vertical dimension relative to the gate structure, increasing the separation distance to reduce capacitance. This allows the device to achieve optimal electrical isolation without proportionally increasing the horizontal device length, maintaining compact packaging.
3Reliability
If multiple gate materials are used to optimize electrical properties, then gate performance improves, but manufacturing complexity increases
Solution Approach 1:
The gate structure is divided into multiple functional layers including conductive material, barrier material, and optional seed layers. Each layer serves a specific purpose: the conductive layer provides electrical function, the barrier layer prevents diffusion, and the seed layer facilitates deposition. This segmentation allows optimization of electrical properties while using standard semiconductor fabrication processes.
Data Source
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Figure 3A~3B
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused metal-oxide semiconductor with one or more gate contacts and methods of manufacture. The structure includes: sidewall spacers over a semiconductor substrate; and a gate structure within a space defined by the sidewall spacers. The gate structure includes: a plurality of gate materials over the semiconductor substrate and between the sidewall spacers; and a gate electrode over the plurality of gate materials and contacting the sidewall spacers.