LDMOS Field Plate Connections for Voltage and Power Loss Tradeoffs
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Solution Overview
Problem
Conventional LDMOS transistor devices face challenges in enhancing electrical performance and reducing power loss in high-voltage semiconductor units, particularly in terms of on-resistance and gate charge, which affect their voltage endurance and efficiency.
Innovation Solution
The semiconductor device incorporates field plates electrically connected to the gate and source regions, allowing for adjustments in on-resistance and gate charge, thereby improving electrical performance and reducing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then high voltage capability is achieved, but on-resistance and gate charge cannot be optimized sufficiently
Solution Approach 1:
The device is divided into multiple independent cell units, each with its own field plates. This segmentation allows each cell to be optimized independently for voltage capability while collectively achieving reduced on-resistance through parallel conduction paths, thereby reducing overall power loss.
Solution Approach 2:
Field plates are added as an additional dimensional feature extending from the gate structure into the drift region. This dimensional addition creates extra electric field control zones that independently manage voltage distribution, enabling simultaneous optimization of voltage capability and resistive losses without compromising the fundamental LDMOS structure.
2Loss of energy
If field plates are added to adjust electrical properties, then on-resistance and gate charge are optimized, but device structure becomes more complex
Solution Approach 1:
The field plates are merged with the existing gate structure, forming an integrated electrode system. This combining approach allows the field plates to be fabricated using the same process steps as the gate, avoiding additional complex manufacturing steps while still providing the electrical optimization benefits of reduced on-resistance and gate charge.
Solution Approach 2:
The gate structure serves dual functions: as the primary control electrode for channel modulation and as the base structure from which field plates extend for electric field management in the drift region. This multi-functionality reduces the need for separate structures, thereby optimizing electrical properties without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The connection of field plates to the gate and source regions enhances the semiconductor device's electrical performance and reduces power loss, addressing the limitations of conventional LDMOS transistor devices.
Implementation Method 1
The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates for adjusting properties of the semiconductor device
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.