LDMOS Gate-Trench Structure for Lower RON and Higher Breakdown
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Solution Overview
Problem
High-voltage laterally diffused metal oxide semiconductor (LDMOS) transistors face challenges in achieving higher breakdown voltage and lower on-resistance (RON) in high-voltage applications.
Innovation Solution
The design involves a gate electrode that downwardly extends into the first well region and is laterally adjacent to the isolation region, with a second gate electrode portion replacing part of the space originally for the isolation region, thereby reducing on-resistance and improving breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode extends downwardly into the first well region and replaces part of the isolation region space, then the on-resistance is reduced and breakdown voltage is improved, but the device structure becomes more complex
Solution Approach 1:
The gate electrode structure transitions from a planar configuration to a three-dimensional configuration by extending downwardly into the first well region. This vertical extension into the depth dimension allows the gate to exert control over a larger volume of the semiconductor structure, improving breakdown voltage and reducing on-resistance through enhanced electric field management in the vertical direction.
Solution Approach 2:
The gate electrode structure merges with the isolation region space by having the second gate electrode portion replace part of the isolation region. This merging consolidates two previously separate functional elements into a unified structure that simultaneously provides gate control and isolation functions, thereby improving performance while managing structural complexity.
2Reliability
If the gate electrode extends downwardly into the first well region, then the on-resistance is reduced, but the manufacturing process becomes more difficult
Solution Approach 1:
The gate electrode structure is formed with its downward extension into the first well region during the preliminary stages of device fabrication, before subsequent processing steps. This preliminary formation of the three-dimensional gate structure allows for optimized doping and insulation layer deposition, facilitating the achievement of lower on-resistance while managing manufacturing complexity through sequential process planning.
Data Source
AI summary
A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.