LDMOS Guard Ring Layout for Smaller Area and Breakdown Voltage
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Solution Overview
Problem
Current LDMOS devices are too large, leading to unsatisfactory on-state breakdown voltage and compatibility in high operational voltage environments.
Innovation Solution
The design incorporates a guard ring surrounding the gate structures and shallow trench isolation (STI) surrounding the guard ring, along with guard regions connecting the source regions to the guard ring, to reduce the overall area of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the LDMOS device uses a conventional structure, then the operational bandwidth and efficiency are maintained, but the device area becomes too large
Solution Approach 1:
The device is segmented into multiple functional regions including a first guard region, second guard region, third guard region, and fourth guard region that are distributed around the gate structure. This segmentation allows for optimized electric field management in different areas, reducing the overall device area while maintaining breakdown voltage characteristics
Solution Approach 2:
Different guard regions are positioned at specific locations with different doping concentrations and geometries to address local electric field requirements. The first guard region has a different configuration than the second guard region, allowing each area to be optimized for its specific function, thereby reducing total device area while maintaining reliability
2Adaptability or versatility
If the LDMOS device uses a conventional structure, then the operational efficiency is maintained, but the compatibility in high operational voltage environments becomes unsatisfactory
Solution Approach 1:
The guard regions extend in multiple dimensions around the gate structure, with some regions positioned at different depths and lateral positions. This multi-dimensional arrangement improves voltage compatibility by managing electric fields in three-dimensional space, reducing the footprint area while enhancing adaptability to high voltage environments
3Reliability
If the LDMOS device reduces its area, then the compatibility improves, but the on-state breakdown voltage becomes unsatisfactory
Solution Approach 1:
Multiple guard regions are merged into a coordinated system that works together to manage the electric field. The first, second, third, and fourth guard regions are positioned and doped to create a unified protective structure that maintains breakdown voltage while minimizing area, achieving both reliability and compactness simultaneously
Data Source
AI summary
A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.