LDMOS Recess Insulator Asymmetry for High-Voltage Reliability
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Solution Overview
Problem
Current integrated circuit devices with LDMOS transistors face challenges in enhancing high voltage characteristics, particularly in mobile devices, where existing designs struggle to optimize the structure of the recess insulating layer for improved performance and reliability.
Innovation Solution
The integrated circuit device incorporates a semiconductor substrate with a fin-type active region, asymmetric recess insulating layers, and a gate electrode layer, where the recess insulating layer has an upper and lower unit with specific lengths and orientations, and the gate electrode layer covers the upper surface and side surfaces of the fin-type active region, enhancing the current path and minimizing hot carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional recess insulating layer structure is used in LDMOS devices, then the device structure is simple, but the high voltage characteristics and reliability are insufficient
Solution Approach 1:
The recess insulating layer is divided into multiple distinct layers: a first recess insulating layer filled in a first recess, a second recess insulating layer filled in a second recess, and a third recess insulating layer filled in a third recess. Each layer has different depths and lateral extents, creating a segmented structure that provides graded electrical isolation and improves high voltage characteristics while managing the complexity through systematic segmentation.
Solution Approach 2:
The recess insulating layer structure employs asymmetric design where the first, second, and third recesses have different depths and lateral extents. The first recess insulating layer extends laterally beyond the second recess insulating layer, which in turn extends beyond the third, creating an asymmetric profile that optimizes the electric field distribution for high voltage operation.
2Reliability
If the recess insulating layer is extended deeper into the drift region, then the high voltage characteristics are improved, but the hot carrier injection increases
Solution Approach 1:
The recess insulating layer is segmented into multiple layers at different depths, with the first recess insulating layer extending deepest, the second at intermediate depth, and the third shallowest. This segmentation allows the insulating structure to provide electrical isolation at multiple depths without requiring a single deep recess that would cause hot carrier injection.
Solution Approach 2:
Different regions of the drift region receive different depths of recess insulating layers tailored to local requirements. The first recess insulating layer provides deep isolation where needed, while the second and third layers provide shallower isolation in other regions, creating local quality variations that improve high voltage characteristics without uniformly increasing hot carrier injection across the entire device.
Data Source
AI summary
An integrated circuit device includes: a semiconductor substrate; first and second conductivity type wells formed in the semiconductor substrate; a source region formed in the second conductivity type well; a drain region formed in the first conductivity type well; a recess insulating layer disposed between the source region and the drain region, and including an upper insulating unit and a lower insulating unit, wherein the upper insulating unit fills an upper substrate recess that extends from an upper surface of the first conductivity type well, and wherein the lower insulating unit fills a lower substrate recess that extends from the upper substrate recess; and a gate electrode layer arranged on the first and second conductivity type wells, and wherein the recess insulating layer has a shape in which both sides thereof are asymmetric with respect to a center of the upper insulating unit.