LDMOS Isolation Region Depleted Well Breakdown Voltage
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Solution Overview
Problem
High-side LDMOS devices face breakdown issues due to increased field stress between the body and buried isolation layer, limiting breakdown voltage and degrading electrostatic discharge (ESD) and safe operating area (SOA) performance, while previous solutions introduce fabrication challenges or degrade performance.
Innovation Solution
The implementation of a partially biased isolation structure using a depleted well region that electrically couples isolation contact regions to doped isolation barriers, reducing voltage stress on isolation regions and enhancing breakdown voltage without increasing device size or fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation regions are biased at drain voltage to deplete drift space, then breakdown voltage is improved, but field stress between body and buried isolation layer increases causing breakdown
Solution Approach 1:
A depleted well region is introduced as an intermediary structure between the isolation contact region and the buried isolation layer. This depleted well acts as a mediator that distributes and reduces the field stress, allowing the isolation regions to be biased at drain voltage for depletion while preventing excessive field stress concentration at the body-buried isolation layer interface.
2Reliability
If previous solutions are implemented to address body-based breakdown, then breakdown voltage is improved, but fabrication complexity increases
Solution Approach 1:
The depleted well region is formed by combining existing doping steps and isolation structures already present in the LDMOS fabrication process. The depleted well is created using the same ion implantation and thermal diffusion processes used for drift region and body region formation, merging multiple functions into existing process steps without adding separate fabrication stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves significantly higher breakdown voltages up to 100 Volts or beyond, while maintaining performance parameters and avoiding degradation of ESD and SOA, by partially lifting the isolation potential and reducing voltage stress between the device body and isolation regions.
Implementation Method 1
a depleted well region disposed in the semiconductor substrate outside of the core device area, the depleted well region electrically coupling the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region
Implementation Method 2
The RESURF structure is designed to deplete the drift space of the LDMOS device in both vertical and lateral directions, thereby reducing the electric field near the surface at the drift region and thus improving the off-state breakdown voltage (BVdss) of the device
Data Source
AI summary
A device formed in a semiconductor substrate is disclosed. The device include a core device formed in the semiconductor substrate, a first deep trench isolation barrier surrounding the core device and a secondary device formed in the semiconductor substrate outside the deep trench isolation barrier. The device also includes a second deep trench isolation barrier formed to isolate the secondary device from remaining part of the semiconductor substrate. A first portion of the secondary device is electrically connected to a first portion of the core device through a first electrical connector and a second portion of the secondary device is electrically connected to a second portion of the core device through a second electrical connector.