LDMOS Isolation Structure With Double-Layer Trench For Electric Field Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional shallow trench isolation structures in LDMOS devices have non-uniform electric field distribution between the source and drain regions, leading to potential lateral voltage breakdown due to concentrated electric fields at the bottom middle position and corners of the trench, which affects device performance.
Innovation Solution
A method involving the formation of a double-layer trench isolation structure, where a first trench with a wide top and narrow bottom is created, followed by filling with silicon oxide, forming a silicon oxide corner structure, depositing a nitrogen-containing compound, and using it as a mask to etch a second deeper trench, resulting in a structure that widens the depletion region and flattens the electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional shallow trench isolation structure is used, then the device area is reduced and parasitic capacitance is lowered, but the electric field distribution becomes non-uniform causing lateral voltage breakdown
Solution Approach 1:
The patent applies local quality by creating different trench depths at different locations: shallower trenches at corner positions and deeper trenches at middle positions. This non-uniform trench depth structure locally adjusts the electric field distribution, preventing concentration at critical areas while maintaining overall compact device area.
Solution Approach 2:
The isolation structure is segmented into multiple trenches with different depths rather than using a single uniform trench. The trench system is divided into corner trenches and middle trenches, each optimized for its specific location to address the electric field distribution problem while maintaining compact device area.
2Reliability
If the trench depth is increased to improve electric field distribution, then voltage breakdown resistance improves, but the manufacturing complexity increases
Solution Approach 1:
The complex deep trench structure is segmented into multiple shallower trenches at different locations rather than creating one extremely deep trench. This segmentation achieves the voltage breakdown resistance of deep trenches while simplifying manufacturing by using multiple standard-depth etching processes with different masks.
Solution Approach 2:
The patent uses preliminary mask formation and selective etching actions to create the multi-depth trench structure. By pre-forming masks at specific locations before etching, the complex deep trench pattern is achieved through controlled preliminary actions rather than requiring complex real-time manufacturing processes.
3Ease of manufacture
If a uniform trench depth is used, then the manufacturing process is simplified, but electric field concentration occurs at the bottom middle position and corners
Solution Approach 1:
The uniform trench process is segmented into location-specific etching operations. Different mask patterns define different trench depths at corner versus middle positions, allowing the manufacturing process to remain relatively simple while achieving non-uniform electric field distribution control through selective trench depth variation.
Solution Approach 2:
The patent applies local quality by making the trench depth a variable parameter depending on location. Corner trenches have different depths than middle trenches, allowing the electric field distribution to be optimized locally at each position while maintaining overall process simplicity through standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the breakdown voltage and reduces the risk of electric field concentration, improving the uniformity of electric field distribution and preventing voltage breakdown, thereby optimizing device performance.
Implementation Method 1
filling silicon oxide into the first trench by depositing
Implementation Method 2
forming a silicon oxide corner structure at a corner of the top of the first trench by thermal oxidation
Implementation Method 3
depositing a nitrogen-containing compound on the surface of the wafer
Implementation Method 4
dry-etching the nitrogen-containing compound, removing the nitrogen-containing compound on the surface of the silicon oxide in the first trench
Data Source
AI summary
Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.