LDMOS Device High-Potential Isolation Ring Breakdown Voltage
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Solution Overview
Problem
LDMOS devices face limitations in breakdown voltage due to breakdown occurring between the body and the buried isolation layer, which restricts their high-side configuration capabilities in high-voltage/high-current applications.
Innovation Solution
The implementation of a substrate with a buried isolation layer and stacked well regions of opposite conductivity types, along with an extension region and biasing region, enhances breakdown voltage by depleting the extension region and reducing electric field stress, while maintaining low on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain voltage is applied to isolation regions to deplete n-type and p-type regions in double RESURF structure, then the breakdown voltage of the drift region is improved, but the field stress between the body and the buried isolation layer increases causing breakdown
Solution Approach 1:
The isolation structure is segmented into multiple regions: a first isolation region extending from the surface to a first depth, and a second isolation region extending from the first depth to a second depth. This segmentation allows different portions of the isolation structure to be biased at different potentials, distributing the field stress and preventing concentrated breakdown between the body and the buried isolation layer.
Solution Approach 2:
Different regions of the isolation structure are assigned different electrical characteristics and biasing conditions. The first isolation region is biased at a first potential while the second isolation region is biased at a second potential, creating localized quality variations that optimize both depletion of the drift region and reduction of field stress at critical interfaces.
2Adaptability or versatility
If a buried isolation layer is used to achieve high-side configuration, then the device can operate in high-side configuration, but the breakdown voltage is limited by breakdown between the body and the buried isolation layer
Solution Approach 1:
The buried isolation layer is divided into two separately biasable regions (first and second isolation regions) with different potentials. This segmentation enables the isolation structure to simultaneously provide high-side configuration capability while managing field stress to achieve higher breakdown voltage than a single uniform isolation layer could provide.
Solution Approach 2:
The isolation structure transitions from a static, uniformly biased configuration to a dynamic, multi-potential configuration. By applying different potentials to different regions of the isolation structure, the device can dynamically optimize both the high-side configuration operation and the breakdown voltage performance under different operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves breakdown voltage (BVdss) while maintaining low on-resistance (Rdson), enabling LDMOS devices to operate effectively in high-side configurations and high-voltage/high-current applications.
Implementation Method 1
The implementation of a substrate with a buried isolation layer and stacked well regions of opposite conductivity types, along with an extension region and biasing region, enhances breakdown voltage by depleting the extension region and reducing electric field stress
Data Source
AI summary
An LDMOS device implements a substrate having a buried isolation layer, a first well region that incorporates two stacked sub-regions to provide a PN junction with a RESURF effect, and a second well region laterally offset from the first well region. A source region is formed in one of the well regions and a drain region is formed in the other well region. An extension region is disposed immediately adjacent to the first well region and laterally distal to the second well region. An extension biasing region is formed at least partially within the extension region, and is separated from the first well region by a portion of the extension region. One or more metallization structures electrically couple the extension biasing region to the one of the source/drain region in the second well region. A gate structure at least partially overlaps both well regions.