LDMOS Transistor Isolation Segmentation for Resistance and Breakdown
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Solution Overview
Problem
Conventional LDMOS transistors face limitations in achieving high breakdown voltage and low on-state resistance, which restricts their power consumption and operating speed under high voltage conditions.
Innovation Solution
A semiconductor device fabrication method involving a substrate with specific regions and an isolation structure, where the isolation structure is formed using local oxidation of silicon and partially removed to create openings, allowing for the formation of doped regions and a gate structure that covers parts of the substrate and isolation structure, resulting in a device with improved breakdown voltage and reduced on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional LDMOS transistor structure is used, then manufacturing process is simple, but on-state resistance cannot be further reduced
Solution Approach 1:
The transistor structure is divided into three distinct regions (first region, second region, third region) with different isolation structure configurations. The first region has removed isolation structure, the second region retains isolation structure, and the third region has isolation structure, creating segmented functional zones that optimize both low on-state resistance and high breakdown voltage
Solution Approach 2:
Different regions of the transistor are given different local characteristics: the first region is optimized for low resistance with exposed substrate, the second region maintains isolation for voltage breakdown, and the third region provides controlled isolation. This local differentiation allows simultaneous optimization of contradictory performance parameters
2Manufacturing precision
If isolation structure is completely removed, then on-state resistance is reduced, but breakdown voltage decreases
Solution Approach 1:
The isolation structure is segmented rather than completely removed or retained. The first region has removed isolation for low resistance, while the second and third regions maintain isolation structure for breakdown voltage, achieving both requirements through spatial segmentation
Solution Approach 2:
Different local regions have different isolation quality: the first region has no isolation (exposed substrate) to minimize resistance, while the second and third regions have isolation structure to maintain high breakdown voltage. This local quality differentiation resolves the contradiction
3Ease of manufacture
If gate structure covers only substrate, then manufacturing is simple, but device performance is limited
Solution Approach 1:
The gate structure serves multiple functions by covering both the substrate in the first region and the isolation structure in the second region. This multi-functional configuration simultaneously achieves proper electrical control and enhanced device performance without requiring separate structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a significant reduction in on-state resistance by up to 27% and an increase in off-state breakdown voltage by up to 60%, enhancing the overall performance of the LDMOS transistor.
Implementation Method 1
A method of forming the isolation structure includes forming a field oxide layer by using local oxidation of silicon
Data Source
AI summary
A method of fabricating a semiconductor device is provided. A substrate is provided. The substrate includes a first region, a second region and a third region. An isolation structure is formed on the substrate in the first and the second region. A removing process is performed to remove the isolation structure in the first region, so as to form a first opening exposing a top surface of the substrate. A gate structure is formed on the substrate, covering a part of the substrate in the first region and a part of the isolation structure in the second region. A first doped region of a first conductive type is formed at one side of the gate structure in the first region, and a second doped region of the first conductive type is formed in the substrate in the third region.