LDMOS Transistor Leakage Testing via Gate Biasing
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Solution Overview
Problem
The challenge in testing LDMOS transistors is to accurately measure leakage current while minimizing subthreshold currents, which are exacerbated by a low turn-on voltage, making it difficult to distinguish between defective and non-defective transistors, especially when the turn-on voltage is less than that of the intrinsic diode.
Innovation Solution
Applying a negative voltage to the gate of the transistor and strategically biasing it to reduce subthreshold currents, allowing for precise measurement of leakage current through the channel, and determining defectiveness based on these measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the transistor's turn-on voltage is reduced to enable efficient operation, then the transistor efficiency is improved, but the subthreshold leakage current increases making defect detection difficult
Solution Approach 1:
The gate is pre-biased to a voltage between 0V and the threshold voltage before leakage current measurement begins. This preliminary biasing action suppresses subthreshold currents in advance, creating optimal measurement conditions before the actual leakage current test is performed.
Solution Approach 2:
The gate voltage is changed from typical operating levels to a specific bias voltage range (0V to Vth) during measurement. By adjusting this parameter, the transistor operates in a regime where subthreshold leakage is minimized, enabling accurate defect detection while maintaining the low turn-on voltage design.
2Ease of operation
If conventional leakage testing is used on low turn-on voltage transistors, then the testing process is simple, but the measurement accuracy deteriorates due to high subthreshold currents
Solution Approach 1:
The testing method modifies the gate voltage parameter from conventional levels to a bias voltage between 0V and Vth. This parameter change maintains testing simplicity while dramatically improving measurement accuracy by suppressing subthreshold currents that would otherwise mask defect signatures.
3Measurement precision
If high accuracy testing equipment is used to detect defects, then the defect detection accuracy is improved, but the equipment cost and complexity increases
Solution Approach 1:
Instead of upgrading to more complex high-accuracy equipment, the method changes the operating parameter (gate bias voltage) to a regime where subthreshold leakage is naturally suppressed. This allows standard testing equipment to achieve high defect detection accuracy without requiring expensive upgrades.
Solution Approach 2:
The method converts the harmful effect of subthreshold leakage into a beneficial measurement regime. By biasing the gate to suppress subthreshold currents, the natural transistor physics is exploited to reduce background noise, making defect detection easier with standard equipment rather than requiring more complex high-accuracy instruments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the accuracy of defect detection in LDMOS transistors by reducing subthreshold currents, enabling faster and more reliable quality control, thereby improving production yield and reducing the need for high-accuracy testing equipment.
Implementation Method 1
Applying a negative voltage to the gate of the transistor and strategically biasing it to reduce subthreshold currents
Implementation Method 2
applying a positive voltage across the channel of the transistor, measuring current through the channel of the transistor
Data Source
AI summary
A method for testing an LDMOS transistor by measuring leakage current between the source and drain in the presence of a bias voltage. The leakage current is indicative of defects in the structure of the transistor.