LDMOS Level Shift Circuit for Gate Voltage Clamping
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Solution Overview
Problem
The conventional high-voltage CMOS process used in TFT-LCD gate drive circuits results in high-voltage devices being damaged due to excessive gate voltage, leading to instability and failure in BCD process applications, where high integration and low power consumption are required.
Innovation Solution
A level shift circuit comprising LDMOS transistors and clamping/current limiting modules is designed to manage voltage levels effectively, preventing device breakdown and ensuring stable operation between high and low voltage levels, utilizing a specific configuration of transistors and resistors to control signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional level shift circuit structure is used in BCD process, then high integration and low power consumption are achieved, but the high-voltage devices are damaged due to excessive gate voltage
Solution Approach 1:
The patent introduces a level shift circuit as an intermediary component between the low-voltage control logic and the high-voltage LDMOS output stage. This level shift circuit converts the low-voltage control signals to appropriate high-voltage levels that the LDMOS devices can handle without breakdown, while preventing excessive gate voltage that would damage the devices. The intermediary circuit thus protects the high-voltage devices from harmful voltage levels while enabling their proper operation.
Solution Approach 2:
The patent changes the voltage level parameter of the control signals through the level shift circuit. By transforming the voltage levels from low-voltage domain to high-voltage domain with appropriate clamping, the circuit enables the LDMOS devices to operate at their optimal voltage parameters without suffering from over-voltage damage, thus resolving the contradiction between achieving high integration/low power and preventing device damage.
2Device complexity
If HV CMOS process is used, then the high-voltage output circuit is simple and level shift is easy to implement, but the devices have large on-resistance and high power consumption
Solution Approach 1:
The patent changes the transistor type parameter from conventional CMOS to LDMOS (lateral double-diffused metal-oxide-semiconductor) devices. LDMOS devices have fundamentally different electrical parameters including lower on-resistance and higher transconductance, which directly reduce power consumption while maintaining the simplicity of the high-voltage output circuit structure. This parameter change enables the circuit to achieve both low power consumption and structural simplicity.
3Power
If LDMOS devices are used in BCD process, then transconductance increases and on-resistance decreases, but the gate-source breakdown voltage is small making devices vulnerable to damage
Solution Approach 1:
The level shift circuit serves as a protective intermediary between the control logic and the LDMOS gate terminal. It transforms control signals to the precise voltage levels required by LDMOS devices, ensuring the gate-source voltage remains within safe operating limits and prevents breakdown. This intermediary protection enables the circuit to utilize the high power capability of LDMOS devices while protecting against their vulnerability to over-voltage damage.
Solution Approach 2:
The level shift circuit provides beforehand protection by pre-conditioning the control signals before they reach the LDMOS gate terminal. By clamping and limiting the voltage levels in advance, the circuit cushions the LDMOS devices from potential voltage spikes or excessive levels that would cause breakdown, thus protecting the devices before damage can occur while allowing them to operate at their full power capability.
Data Source
AI summary
Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage.