LDMOS Transistor Fabrication with Lightly Doped Source
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Solution Overview
Problem
Conventional LDMOS transistors require complex processes incompatible with sub-micron CMOS processes, disrupting the thermal budget and affecting the performance of digital CMOS transistors, particularly in voltage regulators for low-power devices like laptops and cellular phones.
Innovation Solution
A method for fabricating LDMOS transistors using a process compatible with sub-micron CMOS processes, involving the implantation of a high voltage n-doped n-well, formation of a gate oxide, and specific doping profiles for the source and drain regions, including a lightly doped source and shallow drain, to optimize performance without disrupting the thermal budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor fabrication processes are used, then optimized device performance characteristics are achieved, but the process is incompatible with sub-micron CMOS processes and disrupts the thermal budget
Solution Approach 1:
The patent applies local quality by implementing a specialized fabrication sequence for LDMOS transistors within the broader CMOS process. Specifically, the LDMOS transistor fabrication includes distinct steps such as forming a lightly-doped drain region, implanting a deeply-doped source region, and creating a pinned pseudo-n-epitaxial layer, which are then integrated into the common CMOS process flow. This allows LDMOS devices to have optimized local characteristics while maintaining overall process compatibility.
Solution Approach 2:
The patent segments the LDMOS fabrication process into distinct, manageable steps that can be inserted at appropriate points in the CMOS process flow. The segmentation includes separate steps for: (1) forming the pinned pseudo-n-epitaxial layer, (2) creating the lightly-doped drain, (3) implanting the deeply-doped source, and (4) forming the gate structure. This segmentation enables the complex LDMOS process to be integrated without disrupting the overall CMOS thermal budget and process compatibility.
2Reliability
If complex fabrication processes are used for LDMOS transistors, then optimized tradeoff between on-resistance and breakdown voltage is achieved, but the process complexity increases and is not compatible with standard CMOS foundries
Solution Approach 1:
The patent merges LDMOS fabrication steps with the standard CMOS process flow, combining previously separate processes into a unified fabrication sequence. Key merging points include: integrating the LDMOS lightly-doped drain formation with the CMOS source/drain region formation, combining the LDMOS source implantation with CMOS doping steps, and synchronizing gate oxide formation and gate electrode deposition across both device types. This merging reduces overall process complexity while maintaining the optimized on-resistance and breakdown voltage tradeoff.
Solution Approach 2:
The patent creates a universal fabrication process that can fabricate both LDMOS transistors and standard CMOS transistors using the same process steps and equipment. The process is designed so that a single set of process modules can produce both device types, with the LDMOS-specific steps (such as the pinned pseudo-n-epitaxial layer formation and lightly-doped drain creation) being optional additions to the standard CMOS flow. This universality enables standard CMOS foundries to produce LDMOS devices without requiring separate specialized fabrication lines.
3Productivity
If standard CMOS process steps are used, then mass production efficiency is maintained, but LDMOS specific performance requirements cannot be met
Solution Approach 1:
The patent applies preliminary action by preparing the substrate and forming the pinned pseudo-n-epitaxial layer before proceeding with the main LDMOS fabrication steps. This preliminary preparation includes: (1) forming the pinned pseudo-n-epitaxial layer with controlled thickness and doping concentration to establish the foundation for subsequent processing, (2) defining the LDMOS active regions before CMOS processing begins, and (3) pre-aligning the LDMOS device geometry to match the CMOS process capabilities. These preliminary actions ensure that the substrate is properly prepared to meet LDMOS performance requirements while maintaining compatibility with the subsequent mass production CMOS process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the seamless integration of LDMOS transistors into sub-micron CMOS processes, improving the tradeoff between on-resistance, drain-to-substrate breakdown voltage, and source-to-substrate punch-through breakdown voltage, enhancing the performance of voltage regulators for low-power devices.
Implementation Method 1
implanting, into a surface of the substrate, a high voltage n-doped n-well; implanting, into the source region of the transistor, a p-doped p-body; implanting, only into the source region of the transistor, a n-doped lightly doped source
Data Source
AI summary
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.