LDMOS Mini-Oxide Layer for Breakdown Voltage
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Solution Overview
Problem
Existing laterally diffused metal oxide semiconductor field-effect transistors (LDMOSFETs) face a challenge in achieving high breakdown voltage without increasing the device area, particularly in shallow trench isolation (STI) structures.
Innovation Solution
A method involving the formation of a mini-oxide layer adjacent to the channel region of the STI structure, which includes a polysilicon gate and a gate oxide layer, extending from the second P well to the channel region shallow trench isolation structure, allowing for increased breakdown voltage without expanding the device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a shallow trench isolation structure is used in LDMOSFET, then the device area is reduced, but the off-breakdown voltage is insufficient
Solution Approach 1:
The isolation structure is segmented into two parts: the shallow trench isolation structure and the mini-oxide layer. This segmentation allows each part to perform its specific function - the STI structure provides area reduction while the mini-oxide layer provides the necessary breakdown voltage enhancement without increasing overall device area
Solution Approach 2:
The mini-oxide layer acts as an intermediary element between the shallow trench isolation structure and the active device regions. It mediates the electrical field distribution, providing the necessary breakdown voltage enhancement while allowing the STI structure to maintain its area-reducing function
2Reliability
If the off-breakdown voltage is increased by traditional methods, then the breakdown voltage is improved, but the device area increases
Solution Approach 1:
Instead of increasing breakdown voltage through lateral extension (increasing device area), the solution introduces a vertical dimension by adding the mini-oxide layer above the shallow trench isolation structure. This dimensional transition allows breakdown voltage enhancement without lateral area expansion
Solution Approach 2:
The mini-oxide layer is locally positioned at specific regions where breakdown voltage enhancement is most needed, rather than uniformly increasing the entire device structure. This localized approach provides targeted improvement in off-breakdown voltage without unnecessary area expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a mini-oxide layer at the channel region of the STI structure effectively increases the off-breakdown voltage of LDMOSFETs without increasing the device area, enhancing performance while maintaining compactness.
Implementation Method 1
a thickness of the removed high temperature oxide film by etching is less than a thickness of the high temperature oxide film, such that a region not covered by a photoresist preserves a layer of the high temperature oxide film serving as an etching buffer layer
Implementation Method 2
performing wet etching to remove the etching buffer layer, such that a remaining high temperature oxide film forms a mini-oxide layer under the photoresist
Implementation Method 3
performing lithography and ion implantation for a second N well and a second P well, thereby forming the second N well in the first N well, and forming the second P well in the first P well
Data Source
AI summary
Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).